Publications à Polytechnique

Ces données sont extraites du Répertoire des publications de l'École Polytechnique de Montréal. La liste ci-dessous contient seulement les publications auxquelles a participé le professeur ou le chercheur depuis son entrée en fonction à l’École. De plus, certaines publications ne sont pas dans cette liste, notamment les notes de cours et les rapports techniques internes plus d'information...
1	Blanchette, H.F., Ould-Bachir, T., David, J.-P. (2012). A State-Space Modeling Approach for the Fpga-Based Real-Time Simulation of High Switching Frequency Power Converters. IEEE Transactions on Industrial Electronics, 59(12), p. 4555-4567.
2	Daigneault, M.-A., David, J.P. (2011). A High-Resolution Time-to-Digital Converter on FPGA Using Dynamic Reconfiguration. IEEE Transactions on Instrumentation and Measurement, 60(6), p. 2070-2079.
3	Bergeron, E., Perron, L.D., Feeley, M., David, J.P. (2011). Logarithmic-Time FPGA Bitstream Analysis: A Step Towards JIT Hardware Compilation. ACM Transactions on Reconfigurable Technology and Systems, 4(2).
4	Bachir, T.O., David, J.-P. (2010). Performing Floating-Point Accumulation on a Modern FPGA in Single and Double Precision. 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2010), p. 105-108.
5	Bachir, T.O., David, J.-P., Dufour, C., Belanger, J. (2010). Effective FPGA-Based Electric Motor Modeling With Floating-Point Cores. 36th Annual Conference of IEEE Industrial Electronics, IECON 2010, p. 829-834.
6	Bachir, T.O., David, J.-P. (2010). FPGA-Based Real-Time Simulation of State-Space Models Using Floating-Point Cores. 14th International Power Electronics and Motion Control Conference (EPE, p. 26-31.
7	Daigneault, M., David, J.P. (2010). A Novel 10 Ps Resolution TDC Architecture Implemented in a 130nm Process FPGA. 8th IEEE International NEWCAS Conference (NEWCAS 2010), p. 281-284.
8	Allard, M., Grogan, P., David, J.-P. (2009). A Scalable Architecture for Multivariate Polynomial Evaluation on FPGA. International Conference on Reconfigurable Computing and FPGAs, p. 107-112.
9	Daigneault, M.-A., Langlois, J.M.P., David, J.P. (2008). Application Specific Instruction Set Processor Specialized for Block Motion Estimation. IEEE International Conference on Computer Design, p. 266-271.
10	Bafumba-Lokilo, D., Savaria, Y., David, J.-P. (2008). Generic Crossbar Network on Chip for FPGA MPSoCs. 2008 Joint International IEEE Northeast Workshop on Circuits and Systems (NEWCAS) and TAISA Conference (NEWCAS-TAISA), p. 269-272.
11	Bergeron, E., Feeley, M., David, J.P. (2008). Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs. 17th International Conference on Compiler Construction, CC 2008, p. 178-192.
12	Bergeron, E., Feeley, M., Daigneault, M.-A., David, J.P. (2008). Using Dynamic Reconfiguration to Implement High-Resolution Programmable Delays on an FPGA. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference, NEWCAS-TAISA,, p. 265-268.
13	David, J.P., Kalach, K., Tittley, N. (2007). Hardware Complexity of Modular Multiplication and Exponentiation. IEEE Transactions on Computers, 56(10), p. 1308-1319.
14	Hamine, M., Audet, Y., David, J.-P. (2007). A Real Time Image Reconstruction Algorithm for an Integrated Fingerprint Sensor. IEEE Northeast Workshop on Circuits and Systems. NEWCAS 2007, p. 807-810.