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Jean Pierre David (43)

  • Articles de revue (12)
    • 2018
      • Article de revue
        Gemieux, M., Li, M., Savaria, Y., David, J.-P. & Zhu, G. (2018). A Hybrid Architecture with Low Latency Interfaces Enabling Dynamic Cache Management. IEEE Access. Tiré de https://doi.org/10.1109/ACCESS.2018.2876597
      • Article de revue
        Montano, F., Ould-Bachir, T. & David, J.P. (2018). An evaluation of a high-level synthesis approach to the FPGA-based sub-microsecond real-time simulation of power converters. IEEE Transactions on Industrial Electronics, 65(1), 636-644. Tiré de https://doi.org/10.1109/TIE.2017.2716880
    • 2016
      • Article de revue
        David, J.P. (2016). Low latency and division free Gauss-Jordan solver in floating point arithmetic. Journal of Parallel and Distributed Computing, 106, 185-193. Tiré de https://doi.org/10.1016/j.jpdc.2016.12.013
    • 2015
      • Article de revue
        Larbanet, A., Lerebours, J. & David, J.P. (2015). Detecting very large sets of referenced files at 40/100 GbE, especially MP4 files. Digital Investigation, 14(suppl. 1), S85-S94. Tiré de https://doi.org/10.1016/j.diin.2015.05.011
    • 2014
    • 2013
      • Article de revue
        Bachir, T.O., Dufour, C., Belanger, J., Mahseredjian, J. & David, J.P. (2013). A Fully Automated Reconfigurable Calculation Engine Dedicated to the Real-Time Simulation of High Switching Frequency Power Electronic Circuits. Mathematics and Computers in Simulation, 91, 167-177.
      • Article de revue
        Ould-Bachir, T. & David, J.P. (2013). Self-alignment schemes for the implementation of addition-related floating-point operators. ACM Transactions on Reconfigurable Technology and Systems, 6(1).
    • 2012
      • Article de revue
        Blanchette, H.F., Ould-Bachir, T. & David, J.-P. (2012). A State-Space Modeling Approach for the FPGA-Based Real-Time Simulation of High Switching Frequency Power Converters. IEEE Transactions on Industrial Electronics, 59(12), 4555-4567.
    • 2011
      • Article de revue
        Daigneault, M.-A. & David, J.P. (2011). A high-resolution time-to-digital converter on FPGA using dynamic reconfiguration. IEEE Transactions on Instrumentation and Measurement, 60(6), 2070-2079.
      • Article de revue
        Bergeron, E., Perron, L.D., Feeley, M. & David, J.P. (2011). Logarithmic-Time FPGA Bitstream Analysis: A Step Towards JIT Hardware Compilation. ACM Transactions on Reconfigurable Technology and Systems, 4(2).
    • 2007
      • Article de revue
        David, J.P., Kalach, K. & Tittley, N. (2007). Hardware Complexity of Modular Multiplication and Exponentiation. IEEE Transactions on Computers, 56(10), 1308-1319.
  • Communications de conférence (29)
    • 2017
      • Communication de conférence
        Gémieux, M., Savaria, Y., David, J.P. & Zhu, G. (2017). A cache-coherent heterogeneous architecture for low latency real time applications. Communication présentée à 20th IEEE International Symposium on Real-Time Distributed Computing (ISORC 2017), Toronto, ON, Canada (p. 176-184). Tiré de https://doi.org/10.1109/ISORC.2017.1
      • Communication de conférence
        Khanzadi, H., Savaria, Y. & David, J.P. (2017). A data driven CGRA Overlay Architecture with embedded processors. Communication présentée à 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France (p. 269-272). Tiré de https://doi.org/10.1109/NEWCAS.2017.8010157
    • 2015
      • Communication de conférence
        Courbariaux, M., Bengio, Y. & David, J.-P. (2015). BinaryConnect: Training deep neural networks with binary weights during propagations. Communication présentée à 28th Conference on Advances in Neural Information Processing Systems (NIPS 2015), Montréal, Canada (p. 3105-3113).
      • Communication de conférence
        Daigneault, M.-A. & David, J.P. (2015). Intermediate-level synthesis of a Gauss-Jordan elimination linear solver. Communication présentée à 29th IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW 2015), Hyderabad, India (p. 176-181). Tiré de https://doi.org/10.1109/IPDPSW.2015.98
      • Communication de conférence
        David, J.(2015). Low latency solver for linear equation systems in floating point arithmetic. Communication présentée à International Conference on Reconfigurable Computing and FPGAs (ReConFig 2015), Mexico City, Mexico (p. 7 pages). Tiré de https://doi.org/10.1109/ReConFig.2015.7393326
      • Communication de conférence
        Khanzadi, H., Savaria, Y. & David, J.(2015). Mapping applications on two-level configurable hardware. Communication présentée à NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2015), Montreal, QC, Canada (p. 8 pages). Tiré de https://doi.org/10.1109/AHS.2015.7231167
      • Communication de conférence
        Courbariaux, M., Bengio, Y. & David, J.(2015). Training deep neural networks with low precision multiplications. Communication présentée à International Conference on Learning Representations (ICLR 2015), San Diego, Calif. (p. 10 pages). Tiré de https://arxiv.org/abs/1412.7024v5
    • 2013
      • Communication de conférence
        Daigneault, M.-A. & David, J.P. (2013). Hardware description and synthesis of control-intensive reconfigurable dataflow architectures. Communication présentée à ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2013), Monterey, Calif. (p. 274-275). Tiré de https://doi.org/10.1145/2435264.2435337
      • Communication de conférence
        Daigneault, M.-A. & David, J.P. (2013). High-level description and synthesis of floating-point accumulators on FPGA. Communication présentée à 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2013, Seattle, WA, United states (p. 206-209).
      • Communication de conférence
        David, J.(2013). Max-hashing fragments for large data sets detection. Communication présentée à International Conference on Reconfigurable Computing and FPGAs (ReConFig 2013), Cancun, Mexico (p. 6 pages). Tiré de https://doi.org/10.1109/ReConFig.2013.6732307
    • 2012
      • Communication de conférence
        Ould-Bachir, T., Dufour, C., Belanger, J., Mahseredjian, J. & David, J.-P. (2012). Effective floating-point calculation engines intended for the FPGA-based HIL simulation. Communication présentée à 21st IEEE International Symposium on Industrial Electronics (ISIE 2012), Hangzhou, China (p. 1363-1368).
      • Communication de conférence
        Daigneault, M.-A. & David, J.P. (2012). Raising the abstraction level of HDL for control-dominant applications. Communication présentée à 22nd International Conference on Field Programmable Logic and Applications (FPL 2012), Oslo, Norway (p. 515-518).
      • Communication de conférence
        Daigneault, M.A. & David, J.P. (2012). Synchronized-Transfer-Level Design Methodology Applied to Hardware Matrix Multiplication. Communication présentée à 2012 International Conference on Reconfigurable Computing and Fpgas (Reconfig).
      • Communication de conférence
        Allard, M., Grogan, P., Savaria, Y. & David, J.-P. (2012). Two-level configuration for FPGA: A new design methodology based on a computing fabric. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2012), Seoul, Korea, Republic of (p. 265-268).
    • 2011
      • Communication de conférence
        Ould Bachir, T., Dufour, C., David, J.& Mahseredjian, J. (2011). Floating-Point Engines for the FPGA-Based Real-Time Simulation of Power Electronic Circuits. Communication présentée à International Conference on Power Systems Transients (IPST 2011), Delft, Netherlands (p. 7 pages). Tiré de http://ipstconf.org/papers/Proc_IPST2011/11IPST104.pdf
      • Communication de conférence
        Ould Bachir, T., Dufour, C., David, J.P., Bélanger, J. & Mahseredjian, J. (2011). Reconfigurable floating-point engines for the real-time simulation of PECs: A high-speed PMSM drive case study. Communication présentée à International Conference on Modeling and Simulation of Electric Machines, Converters and Systems (ElectrIMACS 2011), Cergy-Pontoise, France.
    • 2010
      • Communication de conférence
        Daigneault, M. & David, J.P. (2010). A novel 10 ps resolution TDC architecture implemented in a 130nm process FPGA. Communication présentée à 8th IEEE International NEWCAS Conference (NEWCAS 2010), Montreal, Quebec (p. 281-284).
      • Communication de conférence
        Bachir, T.O., David, J.-P., Dufour, C. & Belanger, J. (2010). Effective FPGA-based electric motor modeling with floating-point cores. Communication présentée à 36th Annual Conference of IEEE Industrial Electronics, IECON 2010, Glendale, Arizona, USA (p. 829-834).
      • Communication de conférence
        Bachir, T.O. & David, J.-P. (2010). FPGA-Based Real-Time Simulation of State-Space Models using Floating-Point Cores. Communication présentée à 14th International Power Electronics and Motion Control Conference (EPE/PEMC 2010), Ohrid, Republic of Macedonia (p. 26-31).
      • Communication de conférence
        Bachir, T.O. & David, J.-P. (2010). Performing floating-point Accumulation on a Modern FPGA in Single and Double Precision. Communication présentée à 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2010), Charlotte, North Carolina (p. 105-108).
      • Communication de conférence
        Daigneault, M.-A. & David, J.P. (2010). Towards 5ps resolution TDC on a dynamically reconfigurable FPGA. Communication présentée à 8th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2010), Monterey, California (p. 283). Tiré de https://doi.org/10.1145/1723112.1723161
    • 2009
      • Communication de conférence
        Allard, M., Grogan, P. & David, J.-P. (2009). A scalable architecture for multivariate polynomial evaluation on FPGA. Communication présentée à International Conference on Reconfigurable Computing and FPGAs, Cancun, Mexico (p. 107-112).
      • Communication de conférence
        Bafumba-Lokilo, D., Savaria, Y. & David, J.-P. (2009). Generic array-based MPSoC architecture. Communication présentée à 2nd Microsystems and Nanoelectronics Research Conference, Ottawa, Canada (p. 128-131).
    • 2008
      • Communication de conférence
        Daigneault, M.-A., Langlois, J.M.P. & David, J.P. (2008). Application Specific Instruction set processor specialized for block motion estimation. Communication présentée à IEEE International Conference on Computer Design (ICCD 2008) (p. 266-271).
      • Communication de conférence
        Bafumba-Lokilo, D., Savaria, Y. & David, J.-P. (2008). Generic crossbar network on chip for FPGA MPSoCs. Communication présentée à Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008) (p. 269-272).
      • Communication de conférence
        Bergeron, E., Feeley, M. & David, J.P. (2008). Hardware JIT compilation for off-the-shelf dynamically reconfigurable FPGAs. Communication présentée à 17th International Conference on Compiler Construction, CC 2008, Budapest, Hungary (p. 178-192).
      • Communication de conférence
        Bergeron, E., Feeley, M., Daigneault, M.-A. & David, J.P. (2008). Using dynamic reconfiguration to implement high-resolution programmable Delays on an FPGA. Communication présentée à Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), Montreal, QC, Canada (p. 265-268).
    • 2007
      • Communication de conférence
        Hamine, M., Audet, Y. & David, J.-P. (2007). A real time image reconstruction algorithm for an integrated fingerprint sensor. Communication présentée à IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Canada (p. 807-810).
    • 2004
      • Communication de conférence
        Lapalme, J., Aboulhamid, E.M., Nicolescu, G., Charest, L., Boyer, F.R., David, J.P. & Bois, G. (2004). .Net framework - A solution for the next generation tools for system-level modeling and simulation. Communication présentée à Design, Automation and Test in Europe Conference and Exhibition (DATE 2004), Paris, France (p. 732-733). Tiré de https://doi.org/10.1109/DATE.2004.1268952
  • Chapitres de livre (1)
    • 2015
      • Chapitre de livre
        Saad, H., Dennetière, S., Mahseredjian, J., Ould-Bachir, T. & David, J.P. (2015). Simulation of transients for VSC-HVDC transmission systems based on modular multilevel converters. Dans Transient analysis of power systems (p. 317-359). Wiley. Tiré de https://doi.org/10.1002/9781118694190.ch9
  • Brevets (1)