Elbediwy, M., Pontikakis, B., David, J. P., & Savaria, Y. (2023). A Hardware Architecture of a Dynamic Ranking Packet Scheduler for Programmable Network Devices. IEEE Access, 11, 61422-61436.
Répertoire des expertises
David, Jean Pierre

Répertoire des expertises
David, Jean Pierre
Répertoire des expertises
Publications par type
Article de revue (18)
Communication de conférence (74)
Livre
Chapitre de livre (2)
Brevet (1)
Rapport
Thèse (1)
Ensemble de données
Ressource pédagogique
Image
Enregistrement audio
Enregistrement vidéo
Autre
Jean Pierre David (96)
- Articles de revue (18)
- 2023
Article de revue Article de revue Chiu, T.-Y., Le Ny, J., & David, J. P. (2023). Temporal logic explanations for dynamic decision systems using anchors and Monte Carlo Tree Search. Artificial Intelligence, 318, 21 pages.
- 2021
Article de revue Audet, Y., Bendali, A., & David, J. P. (2021). A CMOS Photodetector for or Direct Color Imaging. IEEE Transactions on Electron Devices, 68(3), 1107-1114.
- 2020
Article de revue Montaño, F., Ould-Bachir, T., & David, J. P. (2020). A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators. Electronics, 9(11), 21 pages.Article de revue Trigui, A., Ali, M., Hached, S., David, J. P., Ammari, A. C., Savaria, Y., & Sawan, M. (2020). Generic Wireless Power Transfer and Data Communication System Based on a Novel Modulation Technique. IEEE Transactions on Circuits and Systems I: Regular Papers, 67(11), 3978-3990.Article de revue Abdelsalam, A. M., Elsheikh, A., Chidambaram, S., David, J. P., & Langlois, J. M. P. (2020). POLYBiNN: Binary Inference Engine for Neural Networks using Decision Trees. Journal of Signal Processing Systems, 92(1), 95-107.
- 2018
Article de revue Gemieux, M., Li, M., Savaria, Y., David, J. P., & Zhu, G. (2018). A Hybrid Architecture with Low Latency Interfaces Enabling Dynamic Cache Management. IEEE Access, 6, 62826-62839.Article de revue Montano, F., Ould-Bachir, T., & David, J. P. (2018). An evaluation of a high-level synthesis approach to the FPGA-based submicrosecond real-time simulation of power converters. IEEE Transactions on Industrial Electronics, 65(1), 636-644.Article de revue Daigneault, M.-A., & David, J. P. (2018). Automated synthesis of streaming transfer level hardware designs. ACM Transactions on Reconfigurable Technology and Systems, 11(2), 1-22.Article de revue Sanchez Correa, R., & David, J. P. (2018). Ultra-low latency communication channels for FPGA-based HPC cluster. Integration, 63, 41-55.
- 2017
Article de revue David, J. P. (2017). Low latency and division free Gauss-Jordan solver in floating point arithmetic. Journal of Parallel and Distributed Computing, 106, 185-193.
- 2015
Article de revue Larbanet, A., Lerebours, J., & David, J. P. (2015). Detecting very large sets of referenced files at 40/100 GbE, especially MP4 files. Digital Investigation, 14(suppl. 1), S85-S94.
- 2014
Article de revue Daigneault, M.-A., & David, J. P. (2014). Fast description and synthesis of control-dominant circuits. Computers and Electrical Engineering, 40(4), 1199-1214.
- 2013
Article de revue Ould-Bachir, T., & David, J. P. (2013). Self-alignment schemes for the implementation of addition-related floating-point operators. ACM Transactions on Reconfigurable Technology and Systems, 6(1), 1-21.
- 2012
Article de revue Blanchette, H. F., Ould-Bachir, T., & David, J. P. (2012). A State-Space Modeling Approach for the FPGA-Based Real-Time Simulation of High Switching Frequency Power Converters. IEEE Transactions on Industrial Electronics, 59(12), 4555-4567.
- 2011
Article de revue Daigneault, M.-A., & David, J. P. (2011). A high-resolution time-to-digital converter on FPGA using dynamic reconfiguration. IEEE Transactions on Instrumentation and Measurement, 60(6), 2070-2079.Article de revue Bergeron, E., Perron, L. D., Feeley, M., & David, J. P. (2011). Logarithmic-Time FPGA Bitstream Analysis: A Step Towards JIT Hardware Compilation. ACM Transactions on Reconfigurable Technology and Systems, 4(2), 1-27.
- 2007
Article de revue David, J. P., Kalach, K., & Tittley, N. (2007). Hardware Complexity of Modular Multiplication and Exponentiation. IEEE Transactions on Computers, 56(10), 1308-1319.
- 2023
- Communications de conférence (74)
- 2023
Communication de conférence Askarihemmat, M., Wagner, S., Bilaniuk, O., Hariri, Y., Savaria, Y., & David, J. P. (janvier 2023). BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU [Communication écrite]. 28th Asia and South Pacific Design Automation Conference (ASP-DAC 2023), Tokyo, Japan.Communication de conférence Hajizadeh, F., Alavoine, L., Ould-Bachir, T., Sirois, F., & David, J. P. (août 2023). FPGA-based FDNE models for the accurate real-time simulation of power systems in aircraft [Présentation]. Dans 12th International Conference on Renewable Energy Research and Application, Oshawa, ON, Canada (5 pages).Communication de conférence Ebrahimi, A., Pullu, V. N., Langlois, J. M. P., & David, J. P. Iterative pruning algorithm for efficient look-up table implementation of binary neural networks [Communication écrite]. 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS 2023), Edinburgh, United Kingdom (5 pages).Communication de conférence Dufour, J., Savaria, Y., & David, J. P. Low-Energy, Scalable, On-demand State-of-charge Estimation System for Li-ion batteries [Communication écrite]. 2023 21st IEEE Interregional NEWCAS Conference (NEWCAS 2023), Edinburgh, United Kingdom (5 pages).Communication de conférence AskariHemmat, M.H., Dupuis, T., Fournier, Y., El Zarif, N., Cavalcante, M., Perotti, M., Gurkaynak, F., Benini, L., Leduc-Primeau, F., Savaria, Y., & David, J. P. Quark: an integer RISC-V vector processor for sub-byte quantized DNN inference [Communication écrite]. 2023 IEEE International Symposium on Circuits and Systems (ISCAS 2023), Monterey, CA, USA (5 pages).Communication de conférence Dupuis, T., Fournier, Y., AskariHemmat, M.H., Zarif, N. E., Leduc-Primeau, F., David, J. P., & Savaria, Y. (juin 2023). Sparq: A Custom RISC-V Vector Processor for Efficient Sub-Byte Quantized Inference [Communication écrite]. 21st IEEE Interregional NEWCAS Conference (NEWCAS 2023), Edinburgh, United Kingdom (5 pages).
- 2022
Communication de conférence Su, M., David, J. P., Savaria, Y., Pontikakis, B., & Luinaud, T. (mai 2022). An FPGA-based HW/SW Co-Verification Environment for Programmable Network Devices [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2022), Austin, TX, USA.Communication de conférence Traore, M., Langlois, J. M. P., & David, J. P. (juin 2022). ASIP accelerator for LUT-based neural networks inference [Communication écrite]. 20th IEEE Interregional NEWCAS Conference (NEWCAS 2022), Quebec City, Qc, Canada.Communication de conférence Ehmer, J., Granado, B., Denoulet, J., Savaria, Y., & David, J. P. (juin 2022). Low complexity shallow neural network with improved false negative rate for cyber intrusion detection systems [Communication écrite]. 20th IEEE Interregional NEWCAS Conference (NEWCAS 2022), Quebec City, Qc, Canada.
- 2021
Communication de conférence AskariHemmat, M.H., Bilaniuk, O., Wagner, S., Savaria, Y., & David, J. P. (mai 2021). RISC-V barrel processor for deep neural network acceleration [Communication écrite]. 53rd IEEE International Symposium on Circuits and Systems (ISCAS 2021), Daegu, Korea (5 pages).
- 2020
Communication de conférence Chidambaram, S., Langlois, J. M. P., & David, J. P. (mars 2020). PoET-BiN : Power Efficient Tiny Binary Neurons [Communication écrite]. 3rd Conference on Machine Learning and Systems (MLSys 2020), Austin, Texas (12 pages).Communication de conférence Askarihemmat, M.H., Bilaniuk, O., Wagner, S., Savaria, Y., & David, J. P. (mai 2020). RISC-V Barrel Processor for Accelerator Control [Communication écrite]. 28th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2020), Fayetteville, AR (1 page).
- 2019
Communication de conférence Montano, F., Ould-Bachir, T., Mahseredjian, J., & David, J. P. (mai 2019). A Low-Latency Reconfigurable Multistage Interconnection Network [Communication écrite]. IEEE Canadian Conference of Electrical and Computer Engineering (CCECE 2019), Edmonton, AB, Canada (4 pages).Communication de conférence Riviello, A., & David, J. P. (septembre 2019). Binary speech features for keyword spotting tasks [Communication écrite]. 20th Annual Conference of the International Speech Communication Association: Crossroads of Speech and Language (INTERSPEECH 2019), Graz, Austria.Communication de conférence Bilaniuk, O., Wagner, S., Savaria, Y., & David, J. P. (mai 2019). Bit-slicing FPGA accelerator for quantized neural networks [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2019), Sapporo, Japan (5 pages).Communication de conférence Boyogueno Bidias, S. P., David, J. P., Savaria, Y., & Plamondon, R. (juin 2019). Combining Interval Arithmetic with the Branch and Bound Algorithm for Delta-lognormal Parameter Extraction [Communication écrite]. International Conference of the International Graphonomics Society, Cancun, Mexico (5 pages).Communication de conférence Abdelsalam, A. M., Elsheikh, A., David, J. P., & Langlois, J. M. P. (octobre 2019). POLYCiNN: Multiclass Binary Inference Engine using Convolutional Decision Forests [Communication écrite]. 13th Conference on Design and Architectures for Signal and Image Processing (DASIP 2019), Montréal, Qc, Canada.Communication de conférence AskariHemmat, M.H., Honari, S., Rouhier, L., Perone, C. S., Cohen-Adad, J., Savaria, Y., & David, J. P. (octobre 2019). U-net fixed-point quantization for medical image segmentation [Communication écrite]. 1st International Workshop on Hardware Aware Learning for Medical Imaging and Computer Assisted Intervention (HAL-MICCAI 2019), Shenzhen, China.
- 2018
Communication de conférence Chidambaram, S., Riviello, A., Langlois, J. M. P., & David, J. P. (octobre 2018). Accelerating the Inference Phase in Ternary Convolutional Neural Networks Using Configurable Processors [Communication écrite]. Conference on Design and Architectures for Signal and Image Processing (DASIP 2018), Porto, Portugal.Communication de conférence Boyogueno Bidias, S. P., David, J. P., Savaria, Y., & Plamondon, R. (mai 2018). On the use of Interval Arithmetic to Bound Delta- Lognormal Rapid Human Movements Models [Communication écrite]. International Conference on Pattern Recognition and Artificial Intelligence (ICPRAI 2018), Montréal, Québec.Communication de conférence Abdelsalam, A. M., Elsheikh, A., David, J. P., & Langlois, J. M. P. (octobre 2018). POLYBiNN: A Scalable and Efficient Combinatorial Inference Engine for Neural Networks on FPGA [Communication écrite]. Conference on Design and Architectures for Signal and Image Processing (DASIP 2018), Porto, Portugal.Communication de conférence Perdigon Romero, F., David, J. P., & Cohen-Adad, J. (août 2018). Vertebral labeling on MRI using deep learning techniques [Résumé]. NeuroInformatics 2018, Montréal, Qc, Canada.
- 2017
Communication de conférence Gémieux, M., Savaria, Y., David, J. P., & Zhu, G. (mai 2017). A cache-coherent heterogeneous architecture for low latency real time applications [Communication écrite]. 20th IEEE International Symposium on Real-Time Distributed Computing (ISORC 2017), Toronto, ON, Canada.Communication de conférence Khanzadi, H., Savaria, Y., & David, J. P. (juin 2017). A data driven CGRA Overlay Architecture with embedded processors [Communication écrite]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France.
- 2015
Communication de conférence Courbariaux, M., Bengio, Y., & David, J. P. (décembre 2015). BinaryConnect: Training deep neural networks with binary weights during propagations [Communication écrite]. 28th Conference on Advances in Neural Information Processing Systems (NIPS 2015), Montréal, Québec.Communication de conférence Daigneault, M.-A., & David, J. P. (mai 2015). Intermediate-level synthesis of a Gauss-Jordan elimination linear solver [Communication écrite]. 29th IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW 2015), Hyderabad, India.Communication de conférence David, J. P. (décembre 2015). Low latency solver for linear equation systems in floating point arithmetic [Communication écrite]. International Conference on Reconfigurable Computing and FPGAs (ReConFig 2015), Mexico City, Mexico (7 pages).Communication de conférence Khanzadi, H., Savaria, Y., & David, J. P. (juin 2015). Mapping applications on two-level configurable hardware [Communication écrite]. NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2015), Montréal, Québec (8 pages).Communication de conférence Courbariaux, M., Bengio, Y., & David, J. P. (mai 2015). Training deep neural networks with low precision multiplications [Communication écrite]. International Conference on Learning Representations (ICLR 2015), San Diego, Calif. (10 pages).
- 2013
Communication de conférence Daigneault, M.-A., & David, J. P. (février 2013). Hardware description and synthesis of control-intensive reconfigurable dataflow architectures [Communication écrite]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2013), Monterey, Calif..Communication de conférence Daigneault, M.-A., & David, J. P. (avril 2013). High-level description and synthesis of floating-point accumulators on FPGA [Communication écrite]. 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2013), Seattle, WA, United states.Communication de conférence David, J. P. (décembre 2013). Max-hashing fragments for large data sets detection [Communication écrite]. International Conference on Reconfigurable Computing and FPGAs (ReConFig 2013), Cancun, Mexico (6 pages).
- 2012
Communication de conférence Ould-Bachir, T., Dufour, C., Belanger, J., Mahseredjian, J., & David, J. P. (mai 2012). Effective floating-point calculation engines intended for the FPGA-based HIL simulation [Communication écrite]. 21st IEEE International Symposium on Industrial Electronics (ISIE 2012), Hangzhou, China.Communication de conférence Daigneault, M.-A., & David, J. P. (août 2012). Raising the abstraction level of HDL for control-dominant applications [Communication écrite]. 22nd International Conference on Field Programmable Logic and Applications (FPL 2012), Oslo, Norway.Communication de conférence Daigneault, M. A., & David, J. P. Synchronized-Transfer-Level Design Methodology Applied to Hardware Matrix Multiplication [Communication écrite]. International Conference on Reconfigurable Computing and Fpgas (Reconfig 2012), Cancun, Mexico (7 pages).Communication de conférence Allard, M., Grogan, P., Savaria, Y., & David, J. P. (mai 2012). Two-level configuration for FPGA: A new design methodology based on a computing fabric [Communication écrite]. IEEE International Symposium on Circuits and Systems (ISCAS 2012), Seoul, Korea, Republic of.
- 2011
Communication de conférence Ould-Bachir, T., Dufour, C., Bélanger, J., Mahseredjian, J., & David, J. P. (juin 2011). A Fully Automated Reconfigurable Calculation Engine Dedicated to the Real-Time Simulation of High Switching Frequency Power Electronic Circuits [Communication écrite]. ELECTRIMACS 2011, Cergy-Pontoise, France. Publié dans Mathematics and Computers in Simulation, 91.Communication de conférence Ould-Bachir, T., Dufour, C., David, J. P., & Mahseredjian, J. (juin 2011). Floating-Point Engines for the FPGA-Based Real-Time Simulation of Power Electronic Circuits [Communication écrite]. International Conference on Power Systems Transients (IPST 2011), Delft, Netherlands (7 pages).Communication de conférence Ould-Bachir, T., Dufour, C., David, J. P., Bélanger, J., & Mahseredjian, J. (juin 2011). Reconfigurable floating-point engines for the real-time simulation of PECs: A high-speed PMSM drive case study [Communication écrite]. International Conference on Modeling and Simulation of Electric Machines, Converters and Systems (ElectrIMACS 2011), Cergy-Pontoise, France.
- 2010
Communication de conférence Daigneault, M., & David, J. P. (juin 2010). A novel 10 ps resolution TDC architecture implemented in a 130nm process FPGA [Communication écrite]. 8th IEEE International NEWCAS Conference (NEWCAS 2010), Montréal, Québec.Communication de conférence Ould-Bachir, T., David, J. P., Dufour, C., & Bélanger, J. (novembre 2010). Effective FPGA-based electric motor modeling with floating-point cores [Communication écrite]. 36th Annual Conference of IEEE Industrial Electronics (IECON 2010), Glendale, Arizona, USA.Communication de conférence Ould-Bachir, T., & David, J. P. (septembre 2010). FPGA-Based Real-Time Simulation of State-Space Models using Floating-Point Cores [Communication écrite]. 14th International Power Electronics and Motion Control Conference (EPE/PEMC 2010), Ohrid, Republic of Macedonia.Communication de conférence Ould-Bachir, T., & David, J. P. (mai 2010). Performing floating-point Accumulation on a Modern FPGA in Single and Double Precision [Communication écrite]. 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2010), Charlotte, North Carolina.Communication de conférence Daigneault, M.-A., & David, J. P. (février 2010). Towards 5ps resolution TDC on a dynamically reconfigurable FPGA [Résumé]. 8th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2010), Monterey, California.
- 2009
Communication de conférence Allard, M., Grogan, P., & David, J. P. (décembre 2009). A scalable architecture for multivariate polynomial evaluation on FPGA [Communication écrite]. International Conference on Reconfigurable Computing and FPGAs (ReConFig 2009), Cancun, Mexico.Communication de conférence Bafumba-Lokilo, D., Savaria, Y., & David, J. P. (octobre 2009). Generic array-based MPSoC architecture [Communication écrite]. 2nd Microsystems and Nanoelectronics Research Conference, Ottawa, Canada.
- 2008
Communication de conférence Daigneault, M.-A., Langlois, J. M. P., & David, J. P. (octobre 2008). Application Specific Instruction set processor specialized for block motion estimation [Communication écrite]. IEEE International Conference on Computer Design (ICCD 2008), Lake Tahoe, CA.Communication de conférence Bafumba-Lokilo, D., Savaria, Y., & David, J. P. (juin 2008). Generic crossbar network on chip for FPGA MPSoCs [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008).Communication de conférence Bergeron, E., Feeley, M., & David, J. P. (mars 2008). Hardware JIT compilation for off-the-shelf dynamically reconfigurable FPGAs [Communication écrite]. 17th International Conference on Compiler Construction (CC 2008), Budapest, Hungary.Communication de conférence Bergeron, E., Feeley, M., Daigneault, M.-A., & David, J. P. (juin 2008). Using dynamic reconfiguration to implement high-resolution programmable Delays on an FPGA [Communication écrite]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), Montréal, Québec.
- 2007
Communication de conférence Hamine, M., Audet, Y., & David, J. P. (août 2007). A real time image reconstruction algorithm for an integrated fingerprint sensor [Communication écrite]. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Québec.Communication de conférence Bergeron, E., Feeley, M., & David, J. P. (août 2007). Toward on-chip JIT synthesis on Xilinx VirtexII-Pro FPGAs [Communication écrite]. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Québec.
- 2006
Communication de conférence Saint-Mleux, X., Feeley, M., & David, J. P. (juin 2006). A scheme compiler for hardware dataflow machines [Communication écrite]. Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2006), Ottawa, Canada (4 pages).Communication de conférence Brassard, O., Rousseau, F., David, J. P., Kastle, M., & Aboulhamid, E. M. (juin 2006). Automatic generation of embedded systems with .NET framework based tools [Communication écrite]. IEEE North-East Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Québec, Canada.Communication de conférence Saint-Mleux, X., Feeley, M., & David, J. P. (septembre 2006). SHard: a scheme to hardware compiler [Communication écrite]. Scheme and Functional Programming, Portland, OR (11 pages).
- 2005
Communication de conférence Kalach, K., & David, J. P. (août 2005). Hardware implementation of large number multiplication by FFT with modular arithmetic [Communication écrite]. 3rd International IEEE-NEWCAS Conference (NEWCAS 2005), Québec, Québec.Communication de conférence Bergeron, E., Saint-Mleux, X., Feeley, M., & David, J. P. (juin 2005). High level synthesis for data-driven applications [Communication écrite]. 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), Montréal, Québec.
- 2004
Communication de conférence David, J. P., & Bergeron, E. (septembre 2004). An intermediate level HDL for system level design [Communication écrite]. 7th Forum on Specification and Design Languages (FDL 2004), Lille, France.Communication de conférence David, J. P., & Bergeron, E. (juillet 2004). A step towards intelligent translation from high-level design to RTL [Communication écrite]. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2004), Banff, Canada.Communication de conférence Ogoubi, E., & David, J. P. (juin 2004). Automatic synthesis from high level ASM to VHDL: a case study [Communication écrite]. 2nd Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec.Communication de conférence Lapalme, J., Aboulhamid, E. M., Nicolescu, G., Charest, L., Boyer, F.-R., David, J. P., & Bois, G. (février 2004). [dot]Net framework - A solution for the next generation tools for system-level modeling and simulation [Communication écrite]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2004), Paris, France.Communication de conférence Lapalme, J., Aboulhamed, E. M., Nicolescu, G., Charest, L., Boyer, F.-R., David, J. P., & Bois, G. (juin 2004). Esys.net: A New Solution for Embedded Systems Modeling and Simulation [Communication écrite]. ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2004), Washington, D.C.. Publié dans ACM Sigplan Notices, 39(7).Communication de conférence Zerarka, M. T., David, J. P., & Aboulhamid, E. M. (juillet 2004). High speed emulation of gene regulatory networks using FPGAs [Communication écrite]. 47th Midwest Symposium on Circuits and Systems (MWSCAS 2004), Hiroshima, Japan.
- 2003
Communication de conférence Sun, L. P., Aboulhamid, E. M., & David, J. P. (décembre 2003). Network on chip using a reconfigurable platform [Communication écrite]. 46th Midwest Symposium on Circuits and Systems (MWSCAS 2003), Cairo, Egypt.
- 2002
Communication de conférence Quisquater, J.-J., Standaert, F.-X., Rouvroy, G., David, J. P., & Legat, J.-D. (septembre 2002). A cryptanalytic time-memory tradeoff: first FPGA implementation [Communication écrite]. 12th International Conference on Field Programmable Logic and Applications (FPL 2002), Montpellier, France.Communication de conférence David, J. P., & Legat, J.-D. (décembre 2002). System C: une perspective pour la conception simultanée logiciel/matériel de systèmes utilisant des ressources synchronisées par les données [Communication écrite]. Journées Francophones sur l'Adéquation Algorithme Architecture (JFAAA 2002), Monastir, Tunisie.
- 2001
Communication de conférence David, J. P., Postiau, T., Fisette, P., & Legat, J.-D. (avril 2001). Implementation of very large dataflow graphs on a reconfigurable architecture for robotic applications [Communication écrite]. 15th International Parallel & Distributed Processing Symposium (IPDPS 2001), San Francisco, CA.
- 2000
Communication de conférence Trullemans-Anckaert, A.-M., Ferreira, R., David, J. P., & Legat, J.-D. (novembre 2000). A multi-FPGA system for prototyping power conscious algorithms [Communication écrite]. 15th Design of Circuit and Integrated Systems Conference (DCIS 2000), Montpellier, France.
- 1998
Communication de conférence David, J. P., & Legat, J.-D. (juin 1998). A data-flow oriented co-design for reconfigurable systems [Communication écrite]. 9th International Workshop on Rapid System Prototyping, Leuven, Belgium.Communication de conférence Legat, J.-D., & David, J. P. (novembre 1998). A FPGA-based implementation of adaptive sound filtering [Communication écrite]. 9th International Conference on Circuits, Systems, and Signal Processing (CSSP 1998), Mierlo, The Netherlands.Communication de conférence Legat, J.-D., & David, J. P. (mars 1998). A multi-FPGA based coprocessor for digital signal processing [Communication écrite]. IEEE Benelux Signal Processing Symposium (SPS 1998), Leuven, Belgium.Communication de conférence Legat, J.-D., & David, J. P. (mai 1998). Design of a multi-FPGA system for rapid prototyping experimentation [Communication écrite]. 2nd European Workshop on Microelectronics Education, Noordwijkerhout, The Netherlands.Communication de conférence Legat, J.-D., & David, J. P. (avril 1998). Programmable architectures for subband coding: FPGA-based systems versus dedicated VLSI chip [Communication écrite]. 2nd IMACS Multiconference on Computational Engineering in Systems Applications (CESA 1998), Nabeul-Hammamet, Tunisia.
- 1997
Communication de conférence David, J. P., & Legat, J.-D. (décembre 1997). A 400Kgates, 8Mbytes SRAM multi-FPGA PCI system [Communication écrite]. International Workshop on Logic and Architecture Synthesis (IWLS 1997), Grenoble, France.
- 2023
- Chapitres de livre (2)
- 2021
Chapitre de livre Boyogueno Bidias, S. P., David, J. P., Savaria, Y., & Plamondon, R. (2021). On the use of Interval Arithmetic to Bound Delta- Lognormal Rapid Human Movements Models. Dans The Lognormality Principle and its Applications in e-Security, e-Learning and e-Health (Vol. 88, 309-325).
- 2014
Chapitre de livre Saad, H., Dennetière, S., Mahseredjian, J., Ould-Bachir, T., & David, J. P. (2014). Simulation of transients for VSC-HVDC transmission systems based on modular multilevel converters. Dans Transient analysis of power systems (317-359).
- 2021
- Brevets (1)
- 2016
Brevet David, J. P. (2016). File presence detection and monitoring. (Brevet no US9264434).
- 2016
- Thèses (1)
- 2002
Thèse David, J. P. (2002). Architecture synchronisée par les données pour système reconfigurable [Thèse de doctorat, Université catholique de Louvain].
- 2002