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Jean Pierre David (88)

  • Articles de revue (16)
    • 2021
      • Article de revue
        Audet, Y., Bendali, A. & David, J.P. (2021). A CMOS Photodetector for or Direct Color Imaging. IEEE Transactions on Electron Devices, 68(3), 1107-1114. Tiré de https://doi.org/10.1109/ted.2021.3052717
    • 2020
      • Article de revue
        Montaño, F., Ould-Bachir, T. & David, J.P. (2020). A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators. Electronics, 9(11), 21 pages. Tiré de https://doi.org/10.3390/electronics9111838
      • Article de revue
        Trigui, A., Ali, M., Hached, S., David, J.-P., Ammari, A.C., Savaria, Y. & Sawan, M. (2020). Generic Wireless Power Transfer and Data Communication System Based on a Novel Modulation Technique. IEEE Transactions on Circuits and Systems I: Regular Papers, 67(11), 3978-3990. Tiré de https://doi.org/10.1109/TCSI.2020.3010308
      • Article de revue
        Abdelsalam, A.M., Elsheikh, A., Chidambaram, S., David, J.-P. & Langlois, J.M.P. (2020). POLYBiNN: Binary Inference Engine for Neural Networks using Decision Trees. Journal of Signal Processing Systems, 92(1), 95-107. Tiré de https://doi.org/10.1007/s11265-019-01453-w
    • 2018
      • Article de revue
        Gemieux, M., Li, M., Savaria, Y., David, J.P. & Zhu, G. (2018). A Hybrid Architecture with Low Latency Interfaces Enabling Dynamic Cache Management. IEEE Access, 6, 62826-62839. Tiré de https://doi.org/10.1109/ACCESS.2018.2876597
      • Article de revue
        Montano, F., Ould-Bachir, T. & David, J.P. (2018). An evaluation of a high-level synthesis approach to the FPGA-based submicrosecond real-time simulation of power converters. IEEE Transactions on Industrial Electronics, 65(1), 636-644. Tiré de https://doi.org/10.1109/TIE.2017.2716880
      • Article de revue
        Daigneault, M.-A. & David, J.P. (2018). Automated synthesis of streaming transfer level hardware designs. ACM Transactions on Reconfigurable Technology and Systems, 11(2), 22 pages. Tiré de https://doi.org/10.1145/3243930
    • 2017
      • Article de revue
        David, J.P. (2017). Low latency and division free Gauss-Jordan solver in floating point arithmetic. Journal of Parallel and Distributed Computing, 106, 185-193. Tiré de https://doi.org/10.1016/j.jpdc.2016.12.013
    • 2015
      • Article de revue
        Larbanet, A., Lerebours, J. & David, J.P. (2015). Detecting very large sets of referenced files at 40/100 GbE, especially MP4 files. Digital Investigation, 14(suppl. 1), S85-S94. Tiré de https://doi.org/10.1016/j.diin.2015.05.011
    • 2014
    • 2013
      • Article de revue
        Ould-Bachir, T. & David, J.P. (2013). Self-alignment schemes for the implementation of addition-related floating-point operators. ACM Transactions on Reconfigurable Technology and Systems, 6(1), 21 pages. Tiré de https://doi.org/10.1145/2457443.2457444
    • 2012
      • Article de revue
        Blanchette, H.F., Ould-Bachir, T. & David, J.P. (2012). A State-Space Modeling Approach for the FPGA-Based Real-Time Simulation of High Switching Frequency Power Converters. IEEE Transactions on Industrial Electronics, 59(12), 4555-4567. Tiré de https://doi.org/10.1109/TIE.2011.2182021
    • 2011
      • Article de revue
        Daigneault, M.-A. & David, J.P. (2011). A high-resolution time-to-digital converter on FPGA using dynamic reconfiguration. IEEE Transactions on Instrumentation and Measurement, 60(6), 2070-2079. Tiré de https://doi.org/10.1109/TIM.2011.2115390
      • Article de revue
        Bergeron, E., Perron, L.D., Feeley, M. & David, J.P. (2011). Logarithmic-Time FPGA Bitstream Analysis: A Step Towards JIT Hardware Compilation. ACM Transactions on Reconfigurable Technology and Systems, 4(2), 27 pages. Tiré de https://doi.org/10.1145/1968502.1968503
    • 2007
      • Article de revue
        David, J.P., Kalach, K. & Tittley, N. (2007). Hardware Complexity of Modular Multiplication and Exponentiation. IEEE Transactions on Computers, 56(10), 1308-1319. Tiré de https://doi.org/10.1109/TC.2007.1084
  • Communications de conférence (68)
    • 2022
      • Communication de conférence
        Su, M., David, J.-P., Savaria, Y., Pontikakis, B. & Luinaud, T. (2022). An FPGA-based HW/SW Co-Verification Environment for Programmable Network Devices. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2022), Austin, TX, USA (p. 2529-2533). Tiré de https://doi.org/10.1109/ISCAS48785.2022.9937268
      • Communication de conférence
        Traore, M., Langlois, J.M.P. & David, J.P. (2022). Asip accelerator for LUT-based neural networks inference. Communication présentée à 20th IEEE Interregional NEWCAS Conference (NEWCAS 2022), Quebec City, Qc, Canada (p. 524-528). Tiré de https://doi.org/10.1109/NEWCAS52662.2022.9842211
      • Communication de conférence
        Ehmer, J., Granado, B., Denoulet, J., Savaria, Y. & David, J.-P. (2022). Low complexity shallow neural network with improved false negative rate for cyber intrusion detection systems. Communication présentée à 20th IEEE Interregional NEWCAS Conference (NEWCAS 2022), Quebec City, Qc, Canada (p. 168-172). Tiré de https://doi.org/10.1109/NEWCAS52662.2022.9842204
    • 2021
      • Communication de conférence
        AskariHemmat, M., Bilaniuk, O., Wagner, S., Savaria, Y. & David, J.-P. (2021). RISC-V barrel processor for deep neural network acceleration. Communication présentée à 53rd IEEE International Symposium on Circuits and Systems (ISCAS 2021), Daegu, Korea (5 pages). Tiré de https://doi.org/10.1109/ISCAS51556.2021.9401617
    • 2020
      • Communication de conférence
        Askarihemmat, M., Bilaniuk, O., Wagner, S., Savaria, Y. & David, J.-P. (2020). RISC-V Barrel Processor for Accelerator Control. Communication présentée à 28th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2020), Fayetteville, AR (1 page). Tiré de https://doi.org/10.1109/FCCM48280.2020.00063
    • 2019
      • Communication de conférence
        Montano, F., Ould-Bachir, T., Mahseredjian, J. & David, J.P. (2019). A Low-Latency Reconfigurable Multistage Interconnection Network. Communication présentée à IEEE Canadian Conference of Electrical and Computer Engineering (CCECE 2019), Edmonton, AB, Canada (4 pages). Tiré de https://doi.org/10.1109/CCECE.2019.8861540
      • Communication de conférence
        Riviello, A. & David, J.-P. (2019). Binary speech features for keyword spotting tasks. Communication présentée à 20th Annual Conference of the International Speech Communication Association: Crossroads of Speech and Language (INTERSPEECH 2019), Graz, Austria (p. 3460-3464). Tiré de https://doi.org/10.21437/Interspeech.2019-1877
      • Communication de conférence
        Bilaniuk, O., Wagner, S., Savaria, Y. & David, J.-P. (2019). Bit-slicing FPGA accelerator for quantized neural networks. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2019), Sapporo, Japan (5 pages). Tiré de https://doi.org/10.1109/ISCAS.2019.8702332
      • Communication de conférence
        Boyogueno Bidias, S.P., David, J.P., Savaria, Y. & Plamondon, R. (2019). Combining Interval Arithmetic with the Branch and Bound Algorithm for Delta-lognormal Parameter Extraction. Communication présentée à International Conference of the International Graphonomics Society, Cancun, Mexico (5 pages).
      • Communication de conférence
        Abdelsalam, A.M., Elsheikh, A., David, J.-P. & Langlois, J.M.P. (2019). POLYCiNN: Multiclass Binary Inference Engine using Convolutional Decision Forests. Communication présentée à 13th Conference on Design and Architectures for Signal and Image Processing (DASIP 2019), Montréal, Qc, Canada (p. 13-18). Tiré de https://doi.org/10.1109/DASIP48288.2019.9049176
      • Communication de conférence
        AskariHemmat, M., Honari, S., Rouhier, L., Perone, C.S., Cohen-Adad, J., Savaria, Y. & David, J.-P. (2019). U-net fixed-point quantization for medical image segmentation. Communication présentée à 1st International Workshop on Hardware Aware Learning for Medical Imaging and Computer Assisted Intervention (HAL-MICCAI 2019), Shenzhen, China (p. 115-124). Tiré de https://doi.org/10.1007/978-3-030-33642-4_13
    • 2018
      • Communication de conférence
        Chidambaram, S., Riviello, A., Langlois, J.M.P. & David, J.P. (2018). Accelerating the Inference Phase in Ternary Convolutional Neural Networks Using Configurable Processors. Communication présentée à Conference on Design and Architectures for Signal and Image Processing (DASIP 2018), Porto, Portugal (p. 94-99). Tiré de https://doi.org/10.1109/DASIP.2018.8596860
      • Communication de conférence
        Boyogueno Bidias, S.P., David, J.P., Savaria, Y. & Plamondon, R. (2018). On the use of Interval Arithmetic to Bound Delta- Lognormal Rapid Human Movements Models. Communication présentée à International Conference on Pattern Recognition and Artificial Intelligence (ICPRAI 2018), Montréal, Québec (p. 738-742).
      • Communication de conférence
        Abdelsalam, A.M., Elsheikh, A., David, J.P. & Langlois, J.M.P. (2018). POLYBiNN: A Scalable and Efficient Combinatorial Inference Engine for Neural Networks on FPGA. Communication présentée à Conference on Design and Architectures for Signal and Image Processing (DASIP 2018), Porto, Portugal (p. 19-24). Tiré de https://doi.org/10.1109/DASIP.2018.8596871
      • Communication de conférence
        Perdigon Romero, F., David, J.P. & Cohen-Adad, J. (2018). Vertebral labeling on MRI using deep learning techniques [Résumé]. Présenté à NeuroInformatics 2018, Montréal, Qc, Canada. Tiré de https://space.incf.org/index.php/s/wQiosah6Ul8slk7
    • 2017
      • Communication de conférence
        Gémieux, M., Savaria, Y., David, J.P. & Zhu, G. (2017). A cache-coherent heterogeneous architecture for low latency real time applications. Communication présentée à 20th IEEE International Symposium on Real-Time Distributed Computing (ISORC 2017), Toronto, ON, Canada (p. 176-184). Tiré de https://doi.org/10.1109/ISORC.2017.1
      • Communication de conférence
        Khanzadi, H., Savaria, Y. & David, J.P. (2017). A data driven CGRA Overlay Architecture with embedded processors. Communication présentée à 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France (p. 269-272). Tiré de https://doi.org/10.1109/NEWCAS.2017.8010157
    • 2015
      • Communication de conférence
        Courbariaux, M., Bengio, Y. & David, J.P. (2015). BinaryConnect: Training deep neural networks with binary weights during propagations. Communication présentée à 28th Conference on Advances in Neural Information Processing Systems (NIPS 2015), Montréal, Québec (p. 3105-3113).
      • Communication de conférence
        Daigneault, M.-A. & David, J.P. (2015). Intermediate-level synthesis of a Gauss-Jordan elimination linear solver. Communication présentée à 29th IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW 2015), Hyderabad, India (p. 176-181). Tiré de https://doi.org/10.1109/IPDPSW.2015.98
      • Communication de conférence
        David, J.P. (2015). Low latency solver for linear equation systems in floating point arithmetic. Communication présentée à International Conference on Reconfigurable Computing and FPGAs (ReConFig 2015), Mexico City, Mexico (7 pages). Tiré de https://doi.org/10.1109/ReConFig.2015.7393326
      • Communication de conférence
        Khanzadi, H., Savaria, Y. & David, J.P. (2015). Mapping applications on two-level configurable hardware. Communication présentée à NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2015), Montréal, Québec (8 pages). Tiré de https://doi.org/10.1109/AHS.2015.7231167
      • Communication de conférence
        Courbariaux, M., Bengio, Y. & David, J.P. (2015). Training deep neural networks with low precision multiplications. Communication présentée à International Conference on Learning Representations (ICLR 2015), San Diego, Calif. (10 pages). Tiré de https://arxiv.org/abs/1412.7024v5
    • 2013
      • Communication de conférence
        Ould-Bachir, T., Dufour, C., Belanger, J., Mahseredjian, J. & David, J.P. (2013). A Fully Automated Reconfigurable Calculation Engine Dedicated to the Real-Time Simulation of High Switching Frequency Power Electronic Circuits. Communication présentée à ELECTRIMACS 2011, Cergy-Pontoise, France. (Publié dans Mathematics and Computers in Simulation, 91, 167-177). Tiré de https://doi.org/10.1016/j.matcom.2012.07.021
      • Communication de conférence
        Daigneault, M.-A. & David, J.P. (2013). Hardware description and synthesis of control-intensive reconfigurable dataflow architectures. Communication présentée à ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2013), Monterey, Calif. (p. 274-275). Tiré de https://doi.org/10.1145/2435264.2435337
      • Communication de conférence
        Daigneault, M.-A. & David, J.P. (2013). High-level description and synthesis of floating-point accumulators on FPGA. Communication présentée à 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2013), Seattle, WA, United states (p. 206-209). Tiré de https://doi.org/10.1109/FCCM.2013.37
      • Communication de conférence
        David, J.P. (2013). Max-hashing fragments for large data sets detection. Communication présentée à International Conference on Reconfigurable Computing and FPGAs (ReConFig 2013), Cancun, Mexico (6 pages). Tiré de https://doi.org/10.1109/ReConFig.2013.6732307
    • 2012
      • Communication de conférence
        Ould-Bachir, T., Dufour, C., Belanger, J., Mahseredjian, J. & David, J.P. (2012). Effective floating-point calculation engines intended for the FPGA-based HIL simulation. Communication présentée à 21st IEEE International Symposium on Industrial Electronics (ISIE 2012), Hangzhou, China (p. 1363-1368). Tiré de https://doi.org/10.1109/ISIE.2012.6237289
      • Communication de conférence
        Daigneault, M.-A. & David, J.P. (2012). Raising the abstraction level of HDL for control-dominant applications. Communication présentée à 22nd International Conference on Field Programmable Logic and Applications (FPL 2012), Oslo, Norway (p. 515-518). Tiré de https://doi.org/10.1109/FPL.2012.6339268
      • Communication de conférence
        Daigneault, M.A. & David, J.P. (2012). Synchronized-Transfer-Level Design Methodology Applied to Hardware Matrix Multiplication. Communication présentée à International Conference on Reconfigurable Computing and Fpgas (Reconfig 2012), Cancun, Mexico (7 pages). Tiré de https://doi.org/10.1109/ReConFig.2012.6416789
      • Communication de conférence
        Allard, M., Grogan, P., Savaria, Y. & David, J.P. (2012). Two-level configuration for FPGA: A new design methodology based on a computing fabric. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2012), Seoul, Korea, Republic of (p. 265-268). Tiré de https://doi.org/10.1109/ISCAS.2012.6271851
    • 2011
      • Communication de conférence
        Ould-Bachir, T., Dufour, C., David, J.P. & Mahseredjian, J. (2011). Floating-Point Engines for the FPGA-Based Real-Time Simulation of Power Electronic Circuits. Communication présentée à International Conference on Power Systems Transients (IPST 2011), Delft, Netherlands (7 pages). Tiré de http://ipstconf.org/papers/Proc_IPST2011/11IPST104.pdf
      • Communication de conférence
        Ould-Bachir, T., Dufour, C., David, J.P., Bélanger, J. & Mahseredjian, J. (2011). Reconfigurable floating-point engines for the real-time simulation of PECs: A high-speed PMSM drive case study. Communication présentée à International Conference on Modeling and Simulation of Electric Machines, Converters and Systems (ElectrIMACS 2011), Cergy-Pontoise, France.
    • 2010
      • Communication de conférence
        Daigneault, M. & David, J.P. (2010). A novel 10 ps resolution TDC architecture implemented in a 130nm process FPGA. Communication présentée à 8th IEEE International NEWCAS Conference (NEWCAS 2010), Montréal, Québec (p. 281-284). Tiré de https://doi.org/10.1109/NEWCAS.2010.5603945
      • Communication de conférence
        Ould-Bachir, T., David, J.P., Dufour, C. & Belanger, J. (2010). Effective FPGA-based electric motor modeling with floating-point cores. Communication présentée à 36th Annual Conference of IEEE Industrial Electronics (IECON 2010), Glendale, Arizona, USA (p. 829-834). Tiré de https://doi.org/10.1109/IECON.2010.5675179
      • Communication de conférence
        Ould-Bachir, T. & David, J.P. (2010). FPGA-Based Real-Time Simulation of State-Space Models using Floating-Point Cores. Communication présentée à 14th International Power Electronics and Motion Control Conference (EPE/PEMC 2010), Ohrid, Republic of Macedonia (p. 26-31). Tiré de https://doi.org/10.1109/EPEPEMC.2010.5606584
      • Communication de conférence
        Ould-Bachir, T. & David, J.P. (2010). Performing floating-point Accumulation on a Modern FPGA in Single and Double Precision. Communication présentée à 18th Annual International IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2010), Charlotte, North Carolina (p. 105-108). Tiré de https://doi.org/10.1109/FCCM.2010.24
      • Communication de conférence
        Daigneault, M.-A. & David, J.P. (2010). Towards 5ps resolution TDC on a dynamically reconfigurable FPGA [Résumé]. Présenté à 8th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2010), Monterey, California (p. 283). Tiré de https://doi.org/10.1145/1723112.1723161
    • 2009
      • Communication de conférence
        Allard, M., Grogan, P. & David, J.P. (2009). A scalable architecture for multivariate polynomial evaluation on FPGA. Communication présentée à International Conference on Reconfigurable Computing and FPGAs (ReConFig 2009), Cancun, Mexico (p. 107-112). Tiré de https://doi.org/10.1109/ReConFig.2009.22
      • Communication de conférence
        Bafumba-Lokilo, D., Savaria, Y. & David, J.P. (2009). Generic array-based MPSoC architecture. Communication présentée à 2nd Microsystems and Nanoelectronics Research Conference, Ottawa, Canada (p. 128-131). Tiré de https://doi.org/10.1109/MNRC15848.2009.5338944
    • 2008
      • Communication de conférence
        Daigneault, M.-A., Langlois, J.M.P. & David, J.P. (2008). Application Specific Instruction set processor specialized for block motion estimation. Communication présentée à IEEE International Conference on Computer Design (ICCD 2008), Lake Tahoe, CA (p. 266-271). Tiré de https://doi.org/10.1109/ICCD.2008.4751872
      • Communication de conférence
        Bafumba-Lokilo, D., Savaria, Y. & David, J.P. (2008). Generic crossbar network on chip for FPGA MPSoCs. Communication présentée à Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008) (p. 269-272). Tiré de https://doi.org/10.1109/NEWCAS.2008.4606373
      • Communication de conférence
        Bergeron, E., Feeley, M. & David, J.P. (2008). Hardware JIT compilation for off-the-shelf dynamically reconfigurable FPGAs. Communication présentée à 17th International Conference on Compiler Construction (CC 2008), Budapest, Hungary (p. 178-192). Tiré de https://doi.org/10.1007/978-3-540-78791-4_12
      • Communication de conférence
        Bergeron, E., Feeley, M., Daigneault, M.-A. & David, J.P. (2008). Using dynamic reconfiguration to implement high-resolution programmable Delays on an FPGA. Communication présentée à Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), Montréal, Québec (p. 265-268). Tiré de https://doi.org/10.1109/NEWCAS.2008.4606372
    • 2007
      • Communication de conférence
        Hamine, M., Audet, Y. & David, J.P. (2007). A real time image reconstruction algorithm for an integrated fingerprint sensor. Communication présentée à IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Québec (p. 807-810). Tiré de https://doi.org/10.1109/NEWCAS.2007.4487984
      • Communication de conférence
        Bergeron, E., Feeley, M. & David, J.P. (2007). Toward on-chip JIT synthesis on Xilinx VirtexII-Pro FPGAs. Communication présentée à IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Québec (p. 642-645). Tiré de https://doi.org/10.1109/NEWCAS.2007.4487978
    • 2006
      • Communication de conférence
        Saint-Mleux, X., Feeley, M. & David, J.P. (2006). A scheme compiler for hardware dataflow machines. Communication présentée à Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2006), Ottawa, Canada (4 pages).
      • Communication de conférence
        Brassard, O., Rousseau, F., David, J.P., Kastle, M. & Aboulhamid, E.M. (2006). Automatic generation of embedded systems with .NET framework based tools. Communication présentée à IEEE North-East Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Québec, Canada (p. 165-168). Tiré de https://doi.org/10.1109/NEWCAS.2006.250904
      • Communication de conférence
        Saint-Mleux, X., Feeley, M. & David, J.P. (2006). SHard: a scheme to hardware compiler. Communication présentée à Scheme and Functional Programming, Portland, OR (11 pages).
    • 2005
      • Communication de conférence
        Kalach, K. & David, J.P. (2005). Hardware implementation of large number multiplication by FFT with modular arithmetic. Communication présentée à 3rd International IEEE-NEWCAS Conference (NEWCAS 2005), Québec, Québec (p. 267-270). Tiré de https://doi.org/10.1109/NEWCAS.2005.1496674
      • Communication de conférence
        Bergeron, E., Saint-Mleux, X., Feeley, M. & David, J.P. (2005). High level synthesis for data-driven applications. Communication présentée à 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), Montréal, Québec (p. 54-60). Tiré de https://doi.org/10.1109/RSP.2005.26
    • 2004
      • Communication de conférence
        David, J.P. & Bergeron, E. (2004). An intermediate level HDL for system level design. Communication présentée à 7th Forum on Specification and Design Languages (FDL 2004), Lille, France (p. 526-536).
      • Communication de conférence
        David, J.P. & Bergeron, E. (2004). A step towards intelligent translation from high-level design to RTL. Communication présentée à 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2004), Banff, Canada (p. 183-188). Tiré de https://doi.org/10.1109/IWSOC.2004.1319875
      • Communication de conférence
        Ogoubi, E. & David, J.P. (2004). Automatic synthesis from high level ASM to VHDL: a case study. Communication présentée à 2nd Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec (p. 81-84). Tiré de https://doi.org/10.1109/NEWCAS.2004.1359023
      • Communication de conférence
        Lapalme, J., Aboulhamid, E.M., Nicolescu, G., Charest, L., Boyer, F.R., David, J.P. & Bois, G. (2004). [dot]Net framework - A solution for the next generation tools for system-level modeling and simulation. Communication présentée à Design, Automation and Test in Europe Conference and Exhibition (DATE 2004), Paris, France (p. 732-733). Tiré de https://doi.org/10.1109/DATE.2004.1268952
      • Communication de conférence
        Lapalme, J., Aboulhamed, E.M., Nicolescu, G., Charest, L., Boyer, F.R., David, J.P. & Bois, G. (2004). Esys.net: A New Solution for Embedded Systems Modeling and Simulation. Communication présentée à ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2004), Washington, D.C. (Publié dans ACM Sigplan Notices, 39(7), 107-114). Tiré de https://doi.org/10.1145/997163.997179
      • Communication de conférence
        Zerarka, M.T., David, J.P. & Aboulhamid, E.M. (2004). High speed emulation of gene regulatory networks using FPGAs. Communication présentée à 47th Midwest Symposium on Circuits and Systems (MWSCAS 2004), Hiroshima, Japan (p. I545-I548). Tiré de https://doi.org/10.1109/MWSCAS.2004.1354048
    • 2003
      • Communication de conférence
        Sun, L.P., Aboulhamid, E.M. & David, J.P. (2003). Network on chip using a reconfigurable platform. Communication présentée à 46th Midwest Symposium on Circuits and Systems (MWSCAS 2003), Cairo, Egypt (p. 819-822). Tiré de https://doi.org/10.1109/MWSCAS.2003.1562412
    • 2002
      • Communication de conférence
        Quisquater, J.-J., Standaert, F.-X., Rouvroy, G., David, J.P. & Legat, J.-D. (2002). A cryptanalytic time-memory tradeoff: first FPGA implementation. Communication présentée à 12th International Conference on Field Programmable Logic and Applications (FPL 2002), Montpellier, France (p. 780-789). Tiré de https://doi.org/10.1007/3-540-46117-5_80
      • Communication de conférence
        David, J.P. & Legat, J.-D. (2002). System C: une perspective pour la conception simultanée logiciel/matériel de systèmes utilisant des ressources synchronisées par les données. Communication présentée à Journées Francophones sur l'Adéquation Algorithme Architecture (JFAAA 2002), Monastir, Tunisie.
    • 2001
      • Communication de conférence
        David, J.P., Postiau, T., Fisette, P. & Legat, J.-D. (2001). Implementation of very large dataflow graphs on a reconfigurable architecture for robotic applications. Communication présentée à 15th International Parallel & Distributed Processing Symposium (IPDPS 2001), San Francisco, CA.
    • 2000
      • Communication de conférence
        Trullemans-Anckaert, A.-M., Ferreira, R., David, J.P. & Legat, J.-D. (2000). A multi-FPGA system for prototyping power conscious algorithms. Communication présentée à 15th Design of Circuit and Integrated Systems Conference (DCIS 2000), Montpellier, France.
    • 1998
      • Communication de conférence
        David, J.P. & Legat, J.-D. (1998). A data-flow oriented co-design for reconfigurable systems. Communication présentée à 9th International Workshop on Rapid System Prototyping, Leuven, Belgium (p. 207-211). Tiré de https://doi.org/10.1109/IWRSP.1998.676693
      • Communication de conférence
        Legat, J.-D. & David, J.P. (1998). A FPGA-based implementation of adaptive sound filtering. Communication présentée à 9th International Conference on Circuits, Systems, and Signal Processing (CSSP 1998), Mierlo, The Netherlands (p. 107-111).
      • Communication de conférence
        Legat, J.-D. & David, J.P. (1998). A multi-FPGA based coprocessor for digital signal processing. Communication présentée à IEEE Benelux Signal Processing Symposium (SPS 1998), Leuven, Belgium (p. 59-62).
      • Communication de conférence
        Legat, J.-D. & David, J.P. (1998). Design of a multi-FPGA system for rapid prototyping experimentation. Communication présentée à 2nd European Workshop on Microelectronics Education, Noordwijkerhout, The Netherlands (p. 231-234). Tiré de https://doi.org/10.1007/978-94-011-5110-8_54
      • Communication de conférence
        Legat, J.-D. & David, J.P. (1998). Programmable architectures for subband coding: FPGA-based systems versus dedicated VLSI chip. Communication présentée à 2nd IMACS Multiconference on Computational Engineering in Systems Applications (CESA 1998), Nabeul-Hammamet, Tunisia (p. 231-234).
    • 1997
      • Communication de conférence
        David, J.P. & Legat, J.-D. (1997). A 400Kgates, 8Mbytes SRAM multi-FPGA PCI system. Communication présentée à International Workshop on Logic and Architecture Synthesis (IWLS 1997), Grenoble, France (p. 113-117).
  • Chapitres de livre (2)
    • 2021
      • Chapitre de livre
        Boyogueno Bidias, S.P., David, J.P., Savaria, Y. & Plamondon, R. (2021). On the use of Interval Arithmetic to Bound Delta- Lognormal Rapid Human Movements Models. Dans The Lognormality Principle and its Applications in e-Security, e-Learning and e-Health (Vol. 88, p. 309-325). World Scientific. Tiré de https://doi.org/10.1142/9789811226830_0014
    • 2014
      • Chapitre de livre
        Saad, H., Dennetière, S., Mahseredjian, J., Ould-Bachir, T. & David, J.P. (2014). Simulation of transients for VSC-HVDC transmission systems based on modular multilevel converters. Dans Transient analysis of power systems (p. 317-359). Wiley. Tiré de https://doi.org/10.1002/9781118694190.ch9
  • Brevets (1)
  • Thèses (1)
    • 2002
      • Thèse
        David, J.P. (2002). Architecture synchronisée par les données pour système reconfigurable (Thèse de doctorat, Université catholique de Louvain).