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Yvon Savaria (494)

  • Articles de revue (121)
    • 2018
      • Article de revue
        Lepercq, É., Blaquière, Y. & Savaria, Y. (2018). A pattern-based routing algorithm for a novel electronic system prototyping platform. Integration, 62, 224-237. Tiré de https://doi.org/10.1016/j.vlsi.2018.03.005
      • Article de revue
        Trigui, A., Ali, M., Ammari, A.C., Savaria, Y. & Sawan, M. (2018). A 1.5 pJ/bit, 9.04 Mbit/s Carrier-Width Demodulator for Data Transmission Over an Inductive Link Supporting Power and Data Transfer. IEEE Transactions on Circuits and Systems II: Express Briefs, 1 page. Tiré de https://doi.org/10.1109/TCSII.2018.2864700
      • Article de revue
        Berrima, S., Blaquière, Y. & Savaria, Y. (2018). Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuits. Integration, 62, 159-169. Tiré de https://doi.org/10.1016/j.vlsi.2018.02.010
      • Article de revue
        Hassan, A., Savaria, Y. & Sawan, M. (2018). Electronics and Packaging Intended for Emerging Harsh Environment Applications: A Review. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 14 pages. Tiré de https://doi.org/10.1109/TVLSI.2018.2834499
      • Article de revue
        Vakili, S., Langlois, J.M.P., Savaria, Y. & Manjikian, N. (2018). Enhanced Bloom filter utilisation scheme for string matching using a splitting approach. IET Communications, 12(7), 868-875. Tiré de https://doi.org/10.1049/iet-com.2017.1093
      • Article de revue
        Mohajertehrani, M., Savaria, Y. & Sawan, M. (2018). Harvesting energy from aviation data lines: implementation and experimental results. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(6), 2048-2057. Tiré de https://doi.org/10.1109/TCSI.2017.2769685
    • 2017
      • Article de revue
        Yang, K., Li, M., Zhu, G. & Savaria, Y. (2017). A DAQM-based Load Balancing Scheme for High Performance Computing Platforms. IEEE Access, 5, 22504-22513. Tiré de https://doi.org/10.1109/ACCESS.2017.2760251
      • Article de revue
        Stimpfling, T., Bélanger, N., Cherkaoui, O., Béliveau, A., Béliveau, L. & Savaria, Y. (2017). Extensions to decision-tree based packet classification algorithms to address new classification paradigms. Computer Networks, 122, 83-95. Tiré de https://doi.org/10.1016/j.comnet.2017.04.021
      • Article de revue
        Hoque, K.A., Ait Mohamed, O. & Savaria, Y. (2017). Formal analysis of SEU mitigation for early dependability and performability analysis of FPGA-based space applications. Journal of Applied Logic, 25(47-68). Tiré de https://doi.org/10.1016/j.jal.2017.03.001
      • Article de revue
        Hamad, G.B., Ait Mohamed, O. & Savaria, Y. (2017). Formal Methods Based Synthesis of Single Event Transient Tolerant Combinational Circuits. Journal of Electronic Testing: Theory and Applications, 33(5), 607-620. Tiré de https://doi.org/10.1007/s10836-017-5682-9
      • Article de revue
        Siaka, F., Akbarniai Tehrani, M., Laurin, J.J. & Savaria, Y. (2017). Radar system with enhanced angular resolution based on a novel frequency scanning reflector antenna. IET Radar, Sonar & Navigation, 11(2), 350-358. Tiré de https://doi.org/10.1049/iet-rsn.2016.0320
      • Article de revue
        Li, M., Zhu, G., Savaria, Y. & Lauer, M. (2017). Reliability enhancement of redundancy management in AFDX networks. IEEE Transactions on Industrial Informatics, 13(5), 2118-2129. Tiré de https://doi.org/10.1109/TII.2017.2732345
      • Article de revue
        Ammar, M., Hamad, G.B., Mohamed, O.A. & Savaria, Y. (2017). System-Level Analysis of the Vulnerability of Processors Exposed to Single Event Upsets via Probabilistic Model Checking. IEEE Transactions on Nuclear Science, 64(9), 2523-2530. Tiré de https://doi.org/10.1109/TNS.2017.2736061
    • 2016
      • Article de revue
        Hussain, W., Fakhoury, H., Desgreys, P., Blaquiere, Y. & Savaria, Y. (2016). An asynchronous delta-modulator based A/D converter for an electronic system prototyping platform. IEEE Transactions on Circuits and Systems I: Regular Papers, 63(6), 751-762. Tiré de https://doi.org/10.1109/tcsi.2016.2538019
      • Article de revue
        Hussain, W., Valorge, O., Blaquiere, Y. & Savaria, Y. (2016). A novel spatially configurable differential interface for an electronic system prototyping platform. Integration, the VLSI Journal, 55, 129-137. Tiré de https://doi.org/10.1016/j.vlsi.2016.04.008
      • Article de revue
        Lakhssassi, A., Palenychka, R., Savaria, Y., Sayde, M. & Zaremba, M. (2016). Monitoring thermal stress in wafer-scale integrated circuits by the attentive vision method using an infrared camera. IEEE Transactions on Circuits and Systems for Video Technology, 26(2), 412-424. Tiré de https://doi.org/10.1109/TCSVT.2015.2409632
      • Article de revue
        Tehrani, M.A., Savaria, Y. & Laurin, J.J. (2016). Multiple targets direction-of-arrival estimation in frequency scanning array antennas. IET Radar, Sonar and Navigation, 10(3), 624-631. Tiré de https://doi.org/10.1049/iet-rsn.2015.0401
    • 2015
      • Article de revue
        Hussain, W., Blaquiere, Y. & Savaria, Y. (2015). An interface for open-drain bidirectional communication in field programmable interconnection networks. IEEE Transactions on Circuits and Systems I: Regular Papers, 62(10), 2465-2475. Tiré de https://doi.org/10.1109/TCSI.2015.2476297
      • Article de revue
        Hamad, G.B., Hasan, S.R., Mohamed, O.A. & Savaria, Y. (2015). Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits. Microelectronics Reliability, 55(1), 238-250. Tiré de https://doi.org/10.1016/j.microrel.2014.09.025
    • 2014
      • Article de revue
        Farah, R., Gan, Q., Langlois, J.M.P., Bilodeau, G.-A. & Savaria, Y. (2014). A computationally efficient importance sampling tracking algorithm. Machine Vision and Applications, 25(7), 1761-1777. Tiré de https://doi.org/10.1007/s00138-014-0630-5
      • Article de revue
        Laflamme-Mayer, N., Blaquiere, Y., Savaria, Y. & Sawan, M. (2014). A configurable multi-rail power and I/O pad applied to wafer-scale systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(11), 3135-3144. Tiré de https://doi.org/10.1109/TCSI.2014.2334911
      • Article de revue
        Gan, Q., Langlois, J.M.P. & Savaria, Y. (2014). A Parallel Systematic Resampling Algorithm for High-Speed Particle Filters in Embedded Systems. Circuits, Systems & Signal Processing, 33(11), 3591-3602. Tiré de https://doi.org/10.1007/s00034-014-9820-7
      • Article de revue
        Shaheen, M.A., Savaria, Y. & Hamoui, A.A. (2014). Design and modeling of high-resolution multibit log-domain modulators. Analog Integrated Circuits and Signal Processing, 79(3), 569-582. Tiré de https://doi.org/10.1007/s10470-014-0285-1
      • Article de revue
        Li, M., Lauer, M., Zhu, G. & Savaria, Y. (2014). Determinism enhancement of AFDX networks via frame insertion and sub-virtual link aggregation. IEEE Transactions on Industrial Informatics, 10(3), 1684-1695. Tiré de https://doi.org/10.1109/TII.2014.2315441
      • Article de revue
        Gan, Q.F., Langlois, J.M.P. & Savaria, Y. (2014). Efficient Uniform Quantization Likelihood Evaluation for Particle Filters in Embedded Implementations. Journal of Signal Processing Systems for Signal Image and Video Technology, 75(3), 191-202. Tiré de https://doi.org/10.1007/s11265-013-0798-3
      • Article de revue
        Bany Hamad, G., Hasan, S.R., Mohamed, O.A. & Savaria, Y. (2014). New insights into the single event transient propagation through static and TSPC logic. IEEE Transactions on Nuclear Science, 61(4), 1618-1627. Tiré de https://doi.org/10.1109/TNS.2014.2305434
      • Article de revue
        Tazi, F.Z., Thibeault, C., Savaria, Y., Pichette, S. & Audet, Y. (2014). On extra delays affecting I/O blocks of an SRAM-based FPGA due to ionizing radiation. IEEE Transactions on Nuclear Science, 61(6), 3138-3145. Tiré de https://doi.org/10.1109/TNS.2014.2369417
      • Article de revue
        Kowarzyk, G., Belanger, N., Haccoun, D. & Savaria, Y. (2014). Optimizing the parallel tree-search for finding shortest-span error-correcting CDO codes. IEEE Transactions on Parallel and Distributed Systems, 25(11), 2992-3001. Tiré de https://doi.org/10.1109/TPDS.2013.311
    • 2013
      • Article de revue
        Thibeault, C., Hariri, Y., Hasan, S.R., Hobeika, C., Savaria, Y., Audet, Y. & Tazi, F.Z. (2013). A library-based early soft error sensitivity analysis technique for SRAM-based FPGA design. Journal of Electronic Testing: Theory and Applications, 29(4), 457-471.
      • Article de revue
        Kowarzyk, G., Belanger, N., Haccoun, D. & Savaria, Y. (2013). Efficient parallel search algorithm for determining optimal R=1/2 systematic convolutional self-doubly orthogonal codes. IEEE Transactions on Communications, 61(3), 865-876.
      • Article de revue
        Pons, J.-F., Brault, J.-J. & Savaria, Y. (2013). Modeling, Design and Implementation of a Low-Power Fpga Based Asynchronous Wake-up Receiver for Wireless Applications. Analog Integrated Circuits and Signal Processing, 77(2), 169-182.
      • Article de revue
        Gan, Q., Langlois, J.M.P. & Savaria, Y. (2013). Parallel array histogram architecture for embedded implementations. Electronics Letters, 49(2), 99-101. Tiré de https://doi.org/10.1049/el.2012.2701
    • 2012
      • Article de revue
        Hashemi, S.S., Sawan, M. & Savaria, Y. (2012). A high-efficiency low-voltage CMOS rectifier for harvesting energy in implantable devices. IEEE Transactions on Biomedical Circuits and Systems, 6(4), 326-335.
      • Article de revue
        Trentin, D., Savaria, Y., Zhu, G. & Thibeault, C. (2012). An AFDX Switch Fabric Hardware Core for Avionic Network Prototyping and Characterization. SAE International Journal of Aerospace, 5(1), 181-188.
      • Article de revue
        Tremblay, J.-P., Savaria, Y., Zhu, G., Thibeault, C. & Bouanen, S. (2012). A System Architecture for Smart Sensors Integration in Avionics Applications. SAE International Journal of Aerospace, 5(1), 189-195.
      • Article de revue
        Kowarzyk, G., Belanger, N., Haccoun, D. & Savaria, Y. (2012). Efficient Search Algorithm for Determining Optimal R=1/2 Systematic Convolutional Self-Doubly Orthogonal Codes. IEEE Transactions on Communications, 60(1), 3-8.
      • Article de revue
        Mahvash Mohammadi, H., Savaria, Y. & Langlois, J.M.P. (2012). Enhanced motion compensated deinterlacing algorithm. IET Image Processing, 6(8), 1041-1048. Tiré de https://doi.org/10.1049/iet-ipr.2011.0124
      • Article de revue
        Mbaye, M.M., Belanger, N., Savaria, Y. & Pierre, S. (2012). Loop Acceleration Exploration for ASIP Architecture. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(4), 684-696. Tiré de https://doi.org/10.1109/TVLSI.2011.2107923
      • Article de revue
        Thibeault, C., Pichette, S., Audet, Y., Savaria, Y., Rufenacht, H., Gloutnay, E., Blaquiere, Y., Moupfouma, F. & Batani, N. (2012). On Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiations. IEEE Transactions on Nuclear Science, 59(6), 2959-65.
      • Article de revue
        Nourivand, A., Al-Khalili, A.J. & Savaria, Y. (2012). Postsilicon Tuning of Standby Supply Voltage in Srams to Reduce Yield Losses Due to Parametric Data-Retention Failures. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(1), 29-41.
      • Article de revue
        Aubertin, P., Langlois, J.M.P. & Savaria, Y. (2012). Real-time computation of local neighborhood functions in application-specific instruction-set processors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(11), 2031-2043. Tiré de https://doi.org/10.1109/TVLSI.2011.2170204
      • Article de revue
        Deca, R., Cherkaoui, O. & Savaria, Y. (2012). Rule-based network service provisioning. Journal of Networks, 7(10), 1493-1504.
    • 2011
      • Article de revue
        Singh, R., Audet, Y., Gagnon, Y., Savaria, Y., Boulais, E. & Meunier, M. (2011). A laser-trimmed rail-to-rail precision CMOS operational amplifier. IEEE Transactions on Circuits and Systems II: Express Briefs, 58(2), 75-79.
      • Article de revue
        Hasan, S.R., Belanger, N., Savaria, Y. & Ahmad, M.O. (2011). All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs. Integration, the VLSI Journal, 44(1), 22-38.
      • Article de revue
        Al-Terkawi Hasib, O., Sawan, M. & Savaria, Y. (2011). A low-power asynchronous step-down DCDC converter for implantable devices. IEEE Transactions on Biomedical Circuits and Systems, 5(3), 292-301.
      • Article de revue
        Nourivand, A., Al-Khalili, A.J. & Savaria, Y. (2011). Analysis of resistive open defects in drowsy SRAM cells. Journal of Electronic Testing: Theory and Applications, 27(2), 203-213.
      • Article de revue
        Mahvash Mohammadi, H., Savaria, Y. & Langlois, J.M.P. (2011). Hybrid video deinterlacing algorithm exploiting reverse motion estimation. IET Image Processing, 5(7), 611-618. Tiré de https://doi.org/10.1049/iet-ipr.2010.0111
      • Article de revue
        Boulais, E., Fantoni, J., Chateauneuf, A., Savaria, Y. & Meunier, M. (2011). Laser-induced resistance fine tuning of integrated polysilicon thin-film resistors. IEEE Transactions on Electron Devices, 58(2), 572-575.
    • 2010
      • Article de revue
        Hasan, S.R., Belanger, N., Savaria, Y. & Ahmad, M.O. (2010). Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(10), 2696-707.
      • Article de revue
        Hasan, S.R., Belanger, N., Savaria, Y. & Ahmad, M.O. (2010). Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(8), 2020-2031.
      • Article de revue
        Chebli, R., Sawan, M., El-Sankary, K. & Savaria, Y. (2010). High-voltage DMOS integrated circuits using floating-gate protection technique. Analog Integrated Circuits and Signal Processing, 62(2), 223-235.
      • Article de revue
        Marche, D. & Savaria, Y. (2010). Modeling R-2R segmented-ladder DACs. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(1), 31-43.
    • 2009
      • Article de revue
        Naderi, A., Sawan, M. & Savaria, Y. (2009). A low-power 2 GHz data conversion using delta modulation for portable application. Integration, the VLSI Journal, 42(1), 68-76.
      • Article de revue
        Marche, D., Savaria, Y. & Gagnon, Y. (2009). An improved switch compensation technique for inverted R-2R Ladder DACs. IEEE Transactions on Circuits and Systems I: Regular Papers, 56(6), 1115-1124.
      • Article de revue
        Hashemi, S., Sawan, M. & Savaria, Y. (2009). A novel low-drop CMOS active rectifier for RF-powered devices: Experimental results. Microelectronics Journal, 40(11), 1547-1554.
      • Article de revue
        Tanguay, L.-F., Sawan, M. & Savaria, Y. (2009). A very-high output impedance charge pump for low-voltage low-power PLLs. Microelectronics Journal, 40(6), 1026-1031.
      • Article de revue
        Beucher, N., Belanger, N., Savaria, Y. & Bois, G. (2009). High acceleration for video processing applications using specialized instruction set based on parallelism and data reuse. Journal of Signal Processing Systems, 56(2-3), 155-165.
    • 2008
      • Article de revue
        Bui, H.T. & Savaria, Y. (2008). Design of a High-Speed Differential Frequency-to-Voltage Converter and Its Application in a 5-Ghz Frequency-Locked Loop. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(3), 766-774.
      • Article de revue
        Marche, D., Savaria, Y. & Gagnon, Y. (2008). Laser Fine-Tuneable Deep-Submicrometer Cmos 14-Bit Dac. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(8), 2157-2165.
      • Article de revue
        Naderi, A., Sawan, M. & Savaria, Y. (2008). On the design of undersampling continuous-time bandpass delta - Sigma modulators for gigahertz frequency A/D conversion. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(11), 3488-3499.
      • Article de revue
        Salomon, M.E., Izouggaghen, B., Khouas, A. & Savaria, Y. (2008). Spur Model for a Fixed-Frequency Signal Subject to Periodic Jitter. IEEE Transactions on Instrumentation and Measurement, 57(10), 2320-2328.
      • Article de revue
        Boulais, E., Binet, V., Degorce, J.Y., Wild, G., Savaria, Y. & Meunier, M. (2008). Thermodynamics and Transport Model of Charge Injection in Silicon Irradiated by a Pulsed Focused Laser. IEEE Transactions on Electron Devices, 55(10), 2728-2735.
    • 2007
      • Article de revue
        Mohammadi, H.M., Langlois, J.M.P. & Savaria, Y. (2007). A Five-Field Motion Compensated Deinterlacing Method Based on Vertical Motion. IEEE Transactions on Consumer Electronics, 53(3), 1117-1124. Tiré de https://doi.org/10.1109/TCE.2007.4341594
      • Article de revue
        Gorse, N., Belanger, P., Chureau, A., Aboulhamid, E.M. & Savaria, Y. (2007). A High-Level Requirements Engineering Methodology for Electronic System-Level Design. Computers & Electrical Engineering, 33(4), 249-268.
      • Article de revue
        Mbaye, M.M., Belanger, N., Savaria, Y. & Pierre, S. (2007). A Novel Application-Specific Instruction-Set Processor Design Approach for Video Processing Acceleration. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, 47(3), 297-315.
      • Article de revue
        Deca, R., Cherkaoui, O., Savaria, Y. & Slone, D. (2007). Constraint-Based Model Service for Network Provisioning. Annales des télécommunications, 62(7-8), 847-870.
      • Article de revue
        Saheb, J.-F., Richard, J.-F., Sawan, M., Meingan, R. & Savaria, Y. (2007). System integration of high voltage electrostatic MEMS actuators. Analog Integrated Circuits and Signal Processing, 53(1), 27-34.
    • 2006
      • Article de revue
        Cantin, M.-A., Savaria, Y., Prodanos, D. & Lavoie, P. (2006). A metric for automatic word-length determination of hardware datapaths. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(10), 2228-31.
      • Article de revue
        Nicolescu, B., Ignat, N., Savaria, Y. & Nicolescu, G. (2006). Analysis of real-time systems sensitivity to transient faults using MicroC kernel. IEEE Transactions on Nuclear Science, 53(4), 1902-1909.
      • Article de revue
        Boyer, F.R., Epassa, H.G. & Savaria, Y. (2006). Embedded power-aware cycle by cycle variable speed processor. IEE Proceedings. Computers and Digital Techniques, 153(4), 283-290.
      • Article de revue
        Dubois, M., Savaria, Y., Haccoun, D. & Belanger, N. (2006). Low-power configurable and generic shift register hardware realisations for convolutional encoders and decoders. IEE Proceedings. Circuits, Devices and Systems, 153(3), 207-213.
    • 2005
      • Article de revue
        Khali, H., Savaria, Y. & Houle, J.-L. (2005). A system level implementation strategy and partitioning algorithm for applications based on lookup tables. International Journal of Computer and Electrical Engineering, 31(7), 485-502.
      • Article de revue
        Dubois, M., Savaria, Y., Haccoun, D. & Bélanger, N. (2005). On low power configurable and generic shift register hardware realizations for convolutional encoders and decoders. IEE Proceedings. Circuits, Devices and Systems.
      • Article de revue
        Nicolescu, B., Gorse, N., Savaria, Y., Aboulhamid, E.M. & Velazco, R. (2005). On the Use of Model Checking for the Verification of a Dynamic Signature Monitoring Approach. IEEE Transactions on Nuclear Science, 52(5), 1555-1561.
      • Article de revue
        Chabini, N., Aboulhamid, E.M., Chabini, I. & Savaria, Y. (2005). Scheduling and Optimal Register Placement for Synchronous Circuits Derived Using Software Pipelining Techniques. ACM Transactions on Design Automation of Electronic Systems, 10(2), 187-204.
    • 2004
      • Article de revue
        Cantin, M.A., Savaria, Y. & Velazco, R. (2004). An automatic word length determination method. WSEAS Transactions on Information Science & Applications, 1(5), 1440-1448.
      • Article de revue
        Cantin, M.A., Regimbal, S., Catudal, S. & Savaria, Y. (2004). A Unified Environment to Assess Image Quality in Video Processing. Journal of Circuits, Systems and Computers, 13(6), 1289-1306.
      • Article de revue
        Jiang, Y.T., Wang, Y.K., Song, X.Y. & Savaria, Y. (2004). Computation of Signal Output Probability for Boolean Functions Represented by Obdd. Computers & Mathematics With Applications, 47(12), 1865-1874.
      • Article de revue
        Dubois, M., Bois, G. & Savaria, Y. (2004). Double profiling methodology for video processing platform. WSEAS Transactions on Computers, 3(6), 1802-1807.
      • Article de revue
        Boudjella, A., Jin, Z.F. & Savaria, Y. (2004). Electrical Field Analysis of Nanoscale Field Effect Transistors. Japanese Journal of Applied Physics, 43(6), 3831-3837.
      • Article de revue
        Catudal, S., Cantin, M.-A. & Savaria, Y. (2004). Performance driven validation applied to video processing. WSEAS Transactions on Electronics, 1(3), 568-575.
      • Article de revue
        Nicolescu, B., Savaria, Y. & Velazco, R. (2004). Software detection mechanisms providing full coverage against single bit-flip faults. IEEE Transactions on Nuclear Science, 51(6), 3510-3518.
    • 2003
      • Article de revue
        Beaudin, S., Marceau, R.J., Bois, G., Savaria, Y. & Kandil, N. (2003). An Economic Parallel Processing Technology for Faster Than Real-Time Transient Stability Simulation. European Transactions on Electrical Power, 13(2), 105-112.
      • Article de revue
        Granger, E., Savaria, Y. & Lavoie, P. (2003). A Pattern Reordering Approach Based on Ambiguity Detection for Online Category Learning. IEEE Transactions on Pattern Analysis and Machine Intelligence, 25(4), 524-528.
      • Article de revue
        Khali, H., Savaria, Y., Houle, J.L., Rioux, M., Beraldin, J.A. & Poussart, D. (2003). Improvement of Sensor Accuracy in the Case of a Variable Surface Reflectance Gradient for Active Laser Range Finders. IEEE Transactions on Instrumentation and Measurement, 52(6), 1799-1808.
      • Article de revue
        Chabini, N., Chabini, I., Aboulhamid, E.M. & Savaria, Y. (2003). Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(3), 346-351.
      • Article de revue
        Granger, E., Catudal, S., Grou, R., Mbaye, M.M. & Savaria, Y. (2003). On current strategies for hardware acceleration of digital image restoration filters. WSEAS Transactions on Electronics, 1(3), 551-557.
      • Article de revue
        Catudal, S., Cantin, M.A. & Savaria, Y. (2003). Performance driven validation applied to viseo processing. WSEAS Transactions on Electronics, 1(3), 568-574.
    • 2002
      • Article de revue
        Calbaza, D.E. & Savaria, Y. (2002). A Direct Digital Period Synthesis Circuit. IEEE Journal of Solid-State Circuits, 37(8), 1039-1045.
      • Article de revue
        Meunier, A., Gagnon, Y., Savaria, Y., Lacourse, A. & Cadotte, M. (2002). A novel laser trimming technique for microelectronics. Applied Surface Science, 186(1-4), 52-56.
      • Article de revue
        Jin, Z.-F., Laurin, J.-J. & Savaria, Y. (2002). A practical approach to model long MIS interconnects in VLSI circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10(4), 494-507. Tiré de https://doi.org/10.1109/TVLSI.2002.800520
      • Article de revue
        Loiseau, L. & Savaria, Y. (2002). Methodologies and Strategies for Effective Design Reuse. Canadian Journal of Electrical and Computer Engineering, 27(4), 165-169.
    • 2001
      • Article de revue
        Calbaza, D.E. & Savaria, Y. (2001). Direct Digital Frequency Synthesis of Low-Jitter Clocks. IEEE Journal of Solid-State Circuits, 36(3), 570-572.
      • Article de revue
        Boyer, F.R., Aboulhamid, E.M., Savaria, Y. & Boyer, M. (2001). Optimal Design of Synchronous Circuits Using Software Pipelining Techniques. ACM Transactions on Design Automation of Electronic Systems, 6(4), 516-532.
    • 2000
      • Article de revue
        Donfack, C., Sawan, M. & Savaria, Y. (2000). Implantable Measurement Technique Dedicated to the Monitoring of Electrode-Nerve Contact in Bladder Stimulators. Medical & Biological Engineering & Computing, 38(4), 465-468.
    • 1999
      • Article de revue
        Lavoie, P., Crespo, J.F. & Savaria, Y. (1999). Generalization, Discrimination, and Multiple Categorization Using Adaptive Resonance Theory. IEEE Transactions on Neural Networks, 10(4), 757-767.
      • Article de revue
        Bosi, B., Bois, G. & Savaria, Y. (1999). Reconfigurable Pipelined 2-D Convolvers for Fast Digital Signal Processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7(3), 299-308.
      • Article de revue
        Nekili, M., Savaria, Y. & Bois, G. (1999). Spatial Characterization of Process Variations Via Mos Transistor Time Constants in Vlsi and Wsi. IEEE Journal of Solid-State Circuits, 34(1), 80-84.
    • 1998
      • Article de revue
        Granger, É., Savaria, Y., Lavoie, P. & Cantin, M.A. (1998). Comparison of Self-Organizing Neural Networks for Fast Clustering of Radar Pulses. Signal Processing, 64(3), 249-269.
    • 1997
      • Article de revue
        Granger, É., Savaria, Y., Blaquière, V., Cantin, M.-A. & Lavoie, P. (1997). A VLSI architecture for fast clustering with fuzzy ART neural networks. Journal of Microelectronic Systems Integration, 5(1), 3-18.
      • Article de revue
        Gagnon, Y., Meunier, M., Savaria, Y. & Thibeault, C. (1997). Mathematical cost model for redundant multi-processor arrays. Journal of Microelectronic Systems Integration, 5(4), 199-208.
      • Article de revue
        Nekili, M., Bois, G. & Savaria, Y. (1997). Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 5(2), 161-174.
    • 1996
      • Article de revue
        Abderrahman, A., Savaria, Y. & Kaminska, B. (1996). Analyse, estimation et réduction du bruit de commutation simultanée. [Analysis, estimation and reduction of simultaneous switching noise]. Canadian Journal of Electrical and Computer Engineering, 21(4), 133-143. Tiré de https://doi.org/10.1109/CJECE.1996.7101991
      • Article de revue
        St-Amand, R., Sawan, M. & Savaria, Y. (1996). Design and optimization of a low DC offset CMOS current-source dedicated to implantable miniaturized stimulators. Analog Integrated Circuits and Signal Processing, 11(1), 47-61.
      • Article de revue
        Savaria, Y., Thibeault, C. & Ivanov, A. (1996). Ieee vlsi test symposium - meeting the quality challenge. IEEE Design & Test of Computers, 13(3), 110-112.
      • Article de revue
        Belabbes, N.-E., Guterman, A.J., Savaria, Y. & Dagenais, M. (1996). Ratioed voter circuit for testing and fault-tolerance in VLSI processing arrays. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 43(2), 143-152.
      • Article de revue
        Belhaouane, A., Savaria, Y., Kaminska, B. & Massicotte, D. (1996). Reconstruction method for jitter tolerant data acquisition system. Journal of Electronic Testing: Theory and Applications, 9(1-2), 177-185.
      • Article de revue
        Blaquiere, Y., Dagenais, M. & Savaria, Y. (1996). Timing analysis speed-up using a hierarchical and a multimode approach. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(2), 244-255.
    • 1995
      • Article de revue
        Barwicz, A., Massicotte, D., Savaria, Y., Pango, P.A. & Morawski, R.Z. (1995). An application-specific processor dedicated to kalman-filter-based correction of spectrometric data. IEEE Transactions on Instrumentation and Measurement, 44(3), 720-724.
      • Article de revue
        Blaquiere, T., Gagné, G., Savaria, Y. & Evequoz, C. (1995). A new efficient algorithmic-based seu tolerant system architecture. IEEE Transactions on Nuclear Science, 42(6), 1599-1606.
      • Article de revue
        Belzile, J., Savaria, Y., Haccoun, D. & Chalifoux, M. (1995). Bounds on the performance of partial selection networks. IEEE Transactions on Communications, 43(2-4), 1800-1809.
      • Article de revue
        Thibeault, C., Savaria, Y. & Houle, J.L. (1995). Equivalence proofs of some yield modeling methods for defect-tolerant integrated-circuits. IEEE Transactions on Computers, 44(5), 724-728.
      • Article de revue
        Audet, D. & Savaria, Y. (1995). High-speed interconnections using true single-phase clocking. Journal of Microelectronic Systems Integration, 3(4), 247-257.
      • Article de revue
        Kermouche, R., Audet, D. & Savaria, Y. (1995). On the optimization of integrated hierarchical bus architectures to achieve efficient fault-tolerance. Journal of Microelectronic Systems Integration, 3(1), 47-63.
      • Article de revue
        Soufi, M., Savaria, Y., Darlay, F. & Kaminska, B. (1995). Producing reliable initialization and test of sequential circuits with pseudorandom vectors. IEEE Transactions on Computers, 44(10), 1251-1256.
    • 1994
      • Article de revue
        Thibeault, C., Savaria, Y. & Houle, J.L. (1994). A fast method to evaluate the optimum number of spares in defect-tolerant integrated-circuits. IEEE Transactions on Computers, 43(6), 687-697.
      • Article de revue
        Bélanger, N., Haccoun, D. & Savaria, Y. (1994). A multiprocessor architecture for multiple path stack sequential decoders. IEEE Transactions on Communications, 42(2-4, pt.2), 951-957.
      • Article de revue
        Barwicz, A., Massicotte, D., Savaria, Y., Santerre, M.A. & Morawski, R.Z. (1994). An integrated structure for kalman-filter-based measurand reconstruction. IEEE Transactions on Instrumentation and Measurement, 43(3), 403-410.
      • Article de revue
        Audet, D. & Savaria, Y. (1994). Architectural approach for increasing clock frequency and communication speed in momolithic WSI systems. IEEE Transactions on Components Packaging and Manufacturing Technology. Part B, Advanced Packaging, 17(3), 362-368.
      • Article de revue
        Audet, D., Savaria, Y. & Arel, N. (1994). Pipelining communications in large VLSI/ULSI systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2(1), 1-10.
      • Article de revue
        Lavoie, P., Haccoun, D. & Savaria, Y. (1994). Systolic architecture for fast stack sequential decoders. IEEE Transactions on Communications, 42(2/3/4, pt. 1), 324-335.
  • Communications de conférence (353)
    • 2018
      • Communication de conférence
        Stimpfling, T., Langlois, J.M.P., Bélanger, N. & Savaria, Y. (2018). A low-latency memory-efficient IPv6 lookup engine implemented on FPGA using high-level synthesis. Communication présentée à 18th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid 2018), Washington, D.C.
      • Communication de conférence
        Léonardon, M., Leroux, C., Binet, D., Langlois, J.M.P., Jégo, C. & Savaria, Y. (2018). Custom low power processor for polar decoding. Communication présentée à IEEE International Symposium on Circuits & Systems (ISCAS 2018), Florence, Italy.
      • Communication de conférence
        Meng, L., Guchuan, Z. & Savaria, Y. (2018). Delay bound analysis for heterogeneous multicore systems using network calculus. Communication présentée à 13th IEEE Conference on Industrial Electronics and Applications (ICIEA 2018), Wuhan, China (p. 1825-1830). Tiré de https://doi.org/10.1109/ICIEA.2018.8398005
      • Communication de conférence
        Benacer, I., Boyer, F.-R. & Savaria, Y. (2018). Design of a low latency 40 Gb/s flow-based traffic manager using high-level synthesis. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy (5 pages). Tiré de https://doi.org/10.1109/ISCAS.2018.8351332
      • Communication de conférence
        Hasib, O.A.-T., Crepeau, D., Awad, T., Dulipovici, A., Savaria, Y. & Thibeault, C. (2018). Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits. Communication présentée à 36th IEEE VLSI Test Symposium (VTS 2018), Los Alamitos, CA (6 pages). Tiré de https://doi.org/10.1109/VTS.2018.8368637
      • Communication de conférence
        Abubakr, A., Hassan, A., Ragab, A., Yacout, S., Savaria, Y. & Sawan, M. (2018). High-temperature modeling of the I-V characteristics of GaN150 HEMT using machine learning techniques. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italie (5 pages). Tiré de https://doi.org/10.1109/ISCAS.2018.8351508
      • Communication de conférence
        Fradj, B., Wolff, B., Bélanger, N. & Savaria, Y. (2018). Implementation of a cache-based IPv6 lookup system with hashing. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy (4 pages). Tiré de https://doi.org/10.1109/ISCAS.2018.8351362
    • 2017
      • Communication de conférence
        Gémieux, M., Savaria, Y., David, J.P. & Zhu, G. (2017). A cache-coherent heterogeneous architecture for low latency real time applications. Communication présentée à 20th IEEE International Symposium on Real-Time Distributed Computing (ISORC 2017), Toronto, ON, Canada (p. 176-184). Tiré de https://doi.org/10.1109/ISORC.2017.1
      • Communication de conférence
        Khanzadi, H., Savaria, Y. & David, J.P. (2017). A data driven CGRA Overlay Architecture with embedded processors. Communication présentée à 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France (p. 269-272). Tiré de https://doi.org/10.1109/NEWCAS.2017.8010157
      • Communication de conférence
        Benacer, I., Boyer, F.-R. & Savaria, Y. (2017). A high-speed traffic manager architecture for flow-based networking. Communication présentée à 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France (p. 161-164). Tiré de https://doi.org/10.1109/NEWCAS.2017.8010130
      • Communication de conférence
        Berrima, S., Blaquiere, Y. & Savaria, Y. (2017). A multi-measurements RO-TDC implemented in a Xilinx field programmable gate array. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2017), Baltimore, MD (4 pages). Tiré de https://doi.org/10.1109/ISCAS.2017.8050436
      • Communication de conférence
        Kazma, G., Hamad, G.B., Mohamed, O.A. & Savaria, Y. (2017). Analysis of SEU Propagation in Combinational Circuits at RTL Based on Satisfiability Modulo Theories. Communication présentée à Great Lakes Symposium on VLSI (GLSVLSI 2017), Banff, Alberta (p. 239-244). Tiré de https://doi.org/10.1145/3060403.3060438
      • Communication de conférence
        Kazma, G., Bany Hamad, G., Ait Mohamed, O. & Savaria, Y. (2017). Analysis of SEU propagation in sequential circuits at RTL using Satisfiability Modulo Theories. Communication présentée à 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France (p. 237-240). Tiré de https://doi.org/10.1109/NEWCAS.2017.8010149
      • Communication de conférence
        Luinaud, T., Savaria, Y. & Langlois, J.M.P. (2017). An FPGA Coarse Grained Intermediate Fabric for Regular Expression Search. Communication présentée à Great Lakes Symposium on VLSI (GLSVLSI 2017), Banff, Alberta (p. 423-426). Tiré de https://doi.org/10.1145/3060403.3060429
      • Communication de conférence
        Luinaud, T., Savaria, Y. & Langlois, J.M.P. (2017). An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only). Communication présentée à ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2017), Monterey, California (p. 287-288). Tiré de https://doi.org/10.1145/3020078.3021770
      • Communication de conférence
        Trigui, A., Ali, M., Ammari, A.C., Savaria, Y. & Sawan, M. (2017). A 14.5 W generic carrier width demodulator for telemetry-based medical devices. Communication présentée à 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France (p. 369-372). Tiré de https://doi.org/10.1109/NEWCAS.2017.8010182
      • Communication de conférence
        Hamad, G.B., Kazma, G., Mohamed, O.A. & Savaria, Y. (2017). Comprehensive analysis of sequential circuits vulnerability to transient faults using SMT. Communication présentée à 23rd IEEE International Symposium on On-Line Testing and Robust System Design (IOLTS 2017), Thessaloniki, Greece (p. 33-38). Tiré de https://doi.org/10.1109/IOLTS.2017.8046195
      • Communication de conférence
        Ammar, M., Hamad, G.B., Mohamed, O.A., Savaria, Y. & Velazco, R. (2017). Comprehensive vulnerability analysis of systems exposed to SEUs via probabilistic model checking. Communication présentée à 16th European Conference on Radiation and Its Effects on Components and Systems (RADECS 2016), Bremen, Germany (4 pages). Tiré de https://doi.org/10.1109/RADECS.2016.8093191
      • Communication de conférence
        Fiorentino, M., Savaria, Y. & Thibeault, C. (2017). FPGA implementation of Token-based Self-timed processors: A case study. Communication présentée à 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France (p. 313-316). Tiré de https://doi.org/10.1109/NEWCAS.2017.8010168
      • Communication de conférence
        Ghaffari, A., Leonardon, M., Savaria, Y., Jego, C. & Leroux, C. (2017). Improving performance of SCMA MPA decoders using estimation of conditional probabilities. Communication présentée à 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France (p. 21-24). Tiré de https://doi.org/10.1109/NEWCAS.2017.8010095
      • Communication de conférence
        Hamad, G.B., Mohamed, O.A. & Savaria, Y. (2017). Investigating the efficiency of cell level hardening techniques of single event transients via SMT. Communication présentée à 16th European Conference on Radiation and Its Effects on Components and Systems (RADECS 2016), Bremen, Germany (4 pages). Tiré de https://doi.org/10.1109/RADECS.2016.8093201
      • Communication de conférence
        Hoque, F., Savaria, Y. & Cardinal, C. (2017). Joint power control and beamformer design with antenna selection. Communication présentée à 30th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2017), Windsor, ON, Canada. Tiré de https://doi.org/10.1109/CCECE.2017.7946671
      • Communication de conférence
        Sarbishei, I., Vakili, S., Langlois, J.M.P. & Savaria, Y. (2017). Scalable memory-less architecture for string matching with FPGAs. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2017), Baltimore, MD (p. 2118-2121). Tiré de https://doi.org/10.1109/ISCAS.2017.8050818
      • Communication de conférence
        Hassan, A., Ali, M., Trigui, A., Hached, S., Savaria, Y. & Sawan, M. (2017). Stability of GaN150-based HEMT in high temperature up to 400C. Communication présentée à 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France (p. 133-136). Tiré de https://doi.org/10.1109/NEWCAS.2017.8010123
      • Communication de conférence
        Berrima, S., Blaquiere, Y. & Savaria, Y. (2017). Sub-ps resolution programmable delays implemented in a Xilinx FPGA. Communication présentée à 60th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2017), Boston, MA (p. 918-921). Tiré de https://doi.org/10.1109/MWSCAS.2017.8053074
    • 2016
      • Communication de conférence
        Hussain, W., Savaria, Y. & Blaquiere, Y. (2016). A compact spatially configurable differential input stage for a field programmable interconnection network. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montreal, QC (p. 313-316). Tiré de https://doi.org/10.1109/ISCAS.2016.7527233
      • Communication de conférence
        Benacer, I., Boyer, F.-R., Bélanger, N. & Savaria, Y. (2016). A fast systolic priority queue architecture for a flow-based Traffic Manager. Communication présentée à 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages). Tiré de https://doi.org/10.1109/NEWCAS.2016.7604761
      • Communication de conférence
        Hoque, K.A., Mohamed, O.A. & Savaria, Y. (2016). Applying formal verification to early assessment of FPGA-based aerospace applications: Methodology and experience. Communication présentée à Annual IEEE Systems Conference (SysCon 2016), Orlando, Flordia (6 pages). Tiré de https://doi.org/10.1109/SYSCON.2016.7490557
      • Communication de conférence
        Fiorentino, M., Savaria, Y., Thibeault, C. & Gervais, P. (2016). A practical design method for prototyping self-timed processors using FPGAs. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montréal, QC (p. 1754-1757). Tiré de https://doi.org/10.1109/ISCAS.2016.7538907
      • Communication de conférence
        Hamad, G.B., Kazma, G., Mohamed, O.A. & Savaria, Y. (2016). Comprehensive non-functional analysis of combinational circuits vulnerability to single event transients. Communication présentée à Forum on Specification and Design Languages (FDL 2016), Bremen, Germany (7 pages). Tiré de https://doi.org/10.1109/FDL.2016.7880371
      • Communication de conférence
        Tazi, F.Z., Thibeault, C. & Savaria, Y. (2016). Detailed analysis of radiation-induced delays on I/O blocks of an SRAM-based FPGA. Communication présentée à IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2016), Vancouver, British Columbia (5 pages). Tiré de https://doi.org/10.1109/CCECE.2016.7726600
      • Communication de conférence
        Bany Hamad, G., Kazma, G., Mohamed, O.A. & Savaria, Y. (2016). Efficient and accurate analysis of single event transients propagation using SMT-based techniques. Communication présentée à 35th International Conference on Computer-Aided Design (ICCAD 2016), Austin, TX (7 pages). Tiré de https://doi.org/10.1145/2966986.2967027
      • Communication de conférence
        Ammar, M., Hamad, G.B., Mohamed, O.A. & Savaria, Y. (2016). Efficient probabilistic fault tree analysis of safety critical systems via probabilistic model checking. Communication présentée à Forum on Specification and Design Languages (FDL 2016), Bremen, Germany (8 pages). Tiré de https://doi.org/10.1109/FDL.2016.7880373
      • Communication de conférence
        Kazma, G., Hamad, G.B., Mohamed, O.A. & Savaria, Y. (2016). Investigating the efficiency and accuracy of a data type reduction technique for soft error analysis. Communication présentée à IEEE International Conference on Electronics, Circuits and Systems (ICECS 2016), Monte Carlo, Monaco (p. 273-276). Tiré de https://doi.org/10.1109/ICECS.2016.7841185
      • Communication de conférence
        Vakili, S., Langlois, J.M.P., Boughzala, B. & Savaria, Y. (2016). Memory-efficient string matching for intrusion detection systems using a high-precision pattern grouping algorithm. Communication présentée à 12th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2016), Santa Clara, California (p. 37-42). Tiré de https://doi.org/10.1145/2881025.2881031
      • Communication de conférence
        Alizadeh, R. & Savaria, Y. (2016). Performance analysis of a reduced complexity SCMA decoder exploiting a low-complexity maximum-likelihood approximation. Communication présentée à 23rd IEEE International Conference on Electronics Circuits and Systems (ICECS 2016), Monte Carlo, Monaco (p. 253-256). Tiré de https://doi.org/10.1109/ICECS.2016.7841180
      • Communication de conférence
        Alizadeh, R., Belanger, N., Savaria, Y. & Boyer, F.R. (2016). Performance characterization of an SCMA decoder. Communication présentée à 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages). Tiré de https://doi.org/10.1109/NEWCAS.2016.7604820
      • Communication de conférence
        Trigui, A., Ali, M., Ammari, A.C., Savaria, Y. & Sawan, M. (2016). Quad-Level Carrier Width Modulation demodulator for micro-implants. Communication présentée à 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages). Tiré de https://doi.org/10.1109/NEWCAS.2016.7604801
      • Communication de conférence
        Bany Hamad, G., Ait Mohamed, O. & Savaria, Y. (2016). SMT-based reliability-aware synthesis for single event transients tolerant combinational circuits. Communication présentée à Radiation Effects on Components & Systems Conference (RADECS 2016), Bremen, Germany.
      • Communication de conférence
        Khelifi, M., Massicotte, D. & Savaria, Y. (2016). Towards efficient and concurrent FFTs implementation on Intel Xeon/MIC clusters for LTE and HPC. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montréal, QC (p. 2611-2614). Tiré de https://doi.org/10.1109/ISCAS.2016.7539128
      • Communication de conférence
        Hamad, G.B., Mohamed, O.A. & Savaria, Y. (2016). Towards formal abstraction, modeling, and analysis of single event transients at RTL. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montreal, QC (p. 2166-2169). Tiré de https://doi.org/10.1109/ISCAS.2016.7539010
      • Communication de conférence
        Gémieux, M., Savaria, Y., Zhu, G. & Frigon, J.-F. (2016). Towards LTE physical layer virtualization on a COTS multicore platform with efficient scheduling. Communication présentée à 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages). Tiré de https://doi.org/10.1109/NEWCAS.2016.7604823
      • Communication de conférence
        Hasib, O.A.T., Savaria, Y. & Thibeault, C. (2016). WeSPer: a flexible small delay defect quality metric. Communication présentée à 34th IEEE VLSI Test Symposium (VTS 2016), Las Vegas, Nevada (6 pages). Tiré de https://doi.org/10.1109/VTS.2016.7477266
      • Communication de conférence
        Hassan, A., Trigui, A., Shafique, U., Savaria, Y. & Sawan, M. (2016). Wireless power transfer through metallic barriers enclosing a harsh environment, feasibility and preliminary results. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2016), Montréal, QC (p. 2391-2394). Tiré de https://doi.org/10.1109/ISCAS.2016.7539073
    • 2015
      • Communication de conférence
        Nsame, P., Bois, G. & Savaria, Y. (2015). Analysis and characterization of data energy tradeoffs: for VLSI architectural agility in C-RAN platforms. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2015), Lisbon, Portugal (p. 1466-1469). Tiré de https://doi.org/10.1109/ISCAS.2015.7168921
      • Communication de conférence
        Sion, G., Blaquiere, Y. & Savaria, Y. (2015). Defect diagnosis algorithms for a field programmable interconnect network embedded in a very large area integrated circuit. Communication présentée à 21st International On-Line Testing Symposium (IOLTS 2015), Athena Pallas, Greece (p. 83-88). Tiré de https://doi.org/10.1109/IOLTS.2015.7229837
      • Communication de conférence
        Alizadeh, R., Bélanger, N., Savaria, Y. & Frigon, J.F. (2015). DPDK and MKL; enabling technologies for near deterministic cloud-based signal processing. Communication présentée à 13th IEEE International New Circuits and Systems Conference (NEWCAS 2015), Grenoble, France (4 pages). Tiré de https://doi.org/10.1109/NEWCAS.2015.7182086
      • Communication de conférence
        Hamad, G.B., Mohamed, O.A. & Savaria, Y. (2015). Efficient Multilevel Formal Analysis and Estimation of Design Vulnerability to Single Event Transients. Communication présentée à 21st International On-Line Testing Symposium (IOLTS 2015), Athena Pallas, Greece (p. 1-6). Tiré de https://doi.org/10.1109/IOLTS.2015.7229818
      • Communication de conférence
        Mohajertehrani, M., Shafique, U., Savaria, Y. & Sawan, M. (2015). Harvesting energy from data lines for avionics applications: power conversion chain architecture. Communication présentée à 27th International Conference on Microelectronics (ICM 2015), Casablanca, Maroc (p. 55-58). Tiré de https://doi.org/10.1109/ICM.2015.7437986
      • Communication de conférence
        Khanzadi, H., Savaria, Y. & David, J.(2015). Mapping applications on two-level configurable hardware. Communication présentée à NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2015), Montreal, QC, Canada (p. 8 pages). Tiré de https://doi.org/10.1109/AHS.2015.7231167
      • Communication de conférence
        Mirzadeh, Z., Boland, J.F. & Savaria, Y. (2015). Modeling the faulty behaviour of digital designs using a feed forward neural network approach. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2015), Lisbon, Portugal (p. 1518-1521). Tiré de https://doi.org/10.1109/ISCAS.2015.7168934
      • Communication de conférence
        Khelifi, M., Massicotte, D. & Savaria, Y. (2015). Parallel independent FFT implementation on intel processors and Xeon phi for LTE and OFDM systems. Communication présentée à 1st IEEE Nordic Circuits and Systems Conference (NORCAS 2015), Oslo, Norway (4 pages). Tiré de https://doi.org/10.1109/NORCHIP.2015.7364402
      • Communication de conférence
        Abdollahifakhr, H., Bélanger, N., Savaria, Y. & Gagnon, F. (2015). Power-efficient hardware architecture for computing Split-Radix FFTs on highly sparsed spectrum. Communication présentée à 13th IEEE International New Circuits and Systems Conference (NEWCAS 2015), Grenoble, France (4 pages). Tiré de https://doi.org/10.1109/NEWCAS.2015.7182096
      • Communication de conférence
        Fiorentino, M., Al-Terkawi, O., Savaria, Y. & Thibeault, C. (2015). Self-timed circuits FPGA implementation flow. Communication présentée à 13th IEEE International New Circuits and Systems Conference (NEWCAS 2015), Grenoble, France (4 pages). Tiré de https://doi.org/10.1109/NEWCAS.2015.7182063
      • Communication de conférence
        Hoque, K.A., Mohamed, O.A. & Savaria, Y. (2015). Towards an accurate reliability, availability and maintainability analysis approach for satellite systems based on probabilistic model checking. Communication présentée à Design, Automation and Test in Europe Conference and Exhibition (DATE 2015), Grenoble, France (p. 1635-1640). Tiré de https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=7092655
    • 2014
      • Communication de conférence
        Shaheen, M.A., Hamoui, A.A. & Savaria, Y. (2014). A current-output DAC for low-power low-noise log-domain modulators. Communication présentée à 12th IEEE International New Circuits and Systems Conference (NEWCAS 2014), Trois-Rivieres, QC, Canada (p. 281-284). Tiré de https://doi.org/10.1109/NEWCAS.2014.6934037
      • Communication de conférence
        Nsame, P., Bois, G. & Savaria, Y. (2014). Adaptive real-time DSP acceleration for SoC applications. Communication présentée à 57th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2014), College Station, TX (p. 298-301). Tiré de https://doi.org/10.1109/MWSCAS.2014.6908411
      • Communication de conférence
        Nsame, P., Bois, G. & Savaria, Y. (2014). A data-driven energy efficient and flexible compute fabric architecture: For adaptive computing applied to ULSI of FFT. Communication présentée à 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS 2014), Marseille, France (p. 750-753). Tiré de https://doi.org/10.1109/ICECS.2014.7050094
      • Communication de conférence
        Fischer, A., Plamondon, R., Savaria, Y., Riesen, K. & Bunke, H. (2014). A Hausdorff heuristic for efficient computation of graph edit distance. Communication présentée à Joint IAPR International Workshop on Structural, Syntactic, and Statistical Pattern Recognition (S+SSPR 2014), Joensuu, Finland (p. 83-92). Tiré de https://doi.org/10.1007/978-3-662-44415-3_9
      • Communication de conférence
        Keklikian, T., Langlois, J.M.P. & Savaria, Y. (2014). A Memory Transaction Model for Sparse Matrix-Vector Multiplications on GPUs. Communication présentée à 12th IEEE International New Circuits and Systems Conference (NEWCAS 2014), Trois-Rivières, Canada. Tiré de https://doi.org/10.1109/NEWCAS.2014.6934044
      • Communication de conférence
        Deca, R., Cherkaoui, O. & Savaria, Y. (2014). Constraint-based configuration complexity model for autonomic network configuration management. Communication présentée à Global Information Infrastructure and Networking Symposium (GIIS 2014), Montreal, QC, Canada. Tiré de https://doi.org/10.1109/GIIS.2014.6934272
      • Communication de conférence
        Fischer, A., Plamondon, R., O'Reilly, C. & Savaria, Y. (2014). Neuromuscular representation and synthetic generation of handwritten whiteboard notes. Communication présentée à 14th International Conference on Frontiers in Handwriting Recognition (ICFHR 2014), Crete, Greece (p. 222-7). Tiré de https://doi.org/10.1109/ICFHR.2014.45
      • Communication de conférence
        Hoque, K.A., Mohamed, O.A., Savaria, Y. & Thibeault, C. (2014). Probabilistic model checking based DAL analysis to optimize a combined TMR-blind-scrubbing mitigation technique for FPGA-based aerospace applications. Communication présentée à 12th ACM/IEEE International Conference on Methods and Models for System Design (MEMOCODE 2014), Lausanne, Switzerland (p. 175-184). Tiré de https://doi.org/10.1109/MEMCOD.2014.6961856
      • Communication de conférence
        Hamad, G.B., Mohamed, O.A. & Savaria, Y. (2014). Probabilistic model checking of single event transient propagation at RTL level. Communication présentée à 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS 2014), Marseille, France (p. 451-454). Tiré de https://doi.org/10.1109/ICECS.2014.7050019
      • Communication de conférence
        Zarrabi, H., Al-Khalili, A. & Savaria, Y. (2014). Vt-conscious repeater insertion in power-managed VLSI. Communication présentée à International Symposium on Integrated Circuits (ISIC 2014), Singapore (p. 99-102). Tiré de https://doi.org/10.1109/ISICIR.2014.7029470
    • 2013
      • Communication de conférence
        Gill, D.C., Langlois, J.M.P. & Savaria, Y. (2013). Accelerating a modified gaussian pyramid with a customized processor. Communication présentée à Conference on Design and Architectures for Signal and Image Processing (DASIP 2013), Cagliari, Italy (p. 259-264).
      • Communication de conférence
        Trabelsi, A. & Savaria, Y. (2013). A 2D Gaussian smoothing kernel mapped to heterogeneous platforms. Communication présentée à 11th IEEE International New Circuits and Systems Conference (NEWCAS 2013), Paris, France. Tiré de https://doi.org/10.1109/NEWCAS.2013.6573641
      • Communication de conférence
        Tremblay, J., Savaria, Y., Zhu, G., Ghibeault, C. & Bouanen, S. (2013). A hardware prototype for integration, test and validation of avionic networks. Communication présentée à 32nd IEEE/AIAA Digital Avionics Systems Conference (DASC 2013), Syracuse, NY, USA (p. 2D5-1 - 2D5-11).
      • Communication de conférence
        Robache, R., Boland, J.-F., Thibeault, C. & Savaria, Y. (2013). A methodology for system-level fault injection based on gate-level faulty behavior. Communication présentée à 11th IEEE International New Circuits and Systems Conference (NEWCAS 2013), Paris, France.
      • Communication de conférence
        Baratli, K., Lakhssassi, A., Blaquiere, Y. & Savaria, Y. (2013). A netlist pruning tool for an electronic system prototyping platform. Communication présentée à 11th IEEE International New Circuits and Systems Conference (NEWCAS 2013), Paris, France.
      • Communication de conférence
        Tehrani, M.A., Laurin, J.J. & Savaria, Y. (2013). Angular superresolution algorithm for frequency scanning array antennas. Communication présentée à IEEE Radar Conference (RadarCon 2013), Ottawa, ON, Canada. Tiré de https://doi.org/10.1109/RADAR.2013.6586118
      • Communication de conférence
        Hussain, W., Savaria, Y. & Blaquière, Y. (2013). An interface for the I2C protocol in the WaferBoard TM. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2013), Beijing, Chine.
      • Communication de conférence
        Gan, Q., Langlois, J.M.P. & Savaria, Y. (2013). A reformulated systematic resampling algorithm for particle filters and its parallel implementation in an application-specific instruction-set processor. Communication présentée à 56th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2013), Columbus, OH, USA (p. 1415-1418).
      • Communication de conférence
        Lakhssassi, A., Palenychka, R., Sayde, M., Savaria, Y., Zaremba, M. & Kengne, E. (2013). A spatiotemporal attention operator for monitoring thermo-mechanical stress in wafer-scale integrated circuits using an infrared camera. Communication présentée à 8th International Symposium on Image and Signal Processing and Analysis (ISPA 2013), Trieste, Italy (p. 165-70).
      • Communication de conférence
        Al-bayati, Z., Ait Mohamed, O., Rafay Hasan, S. & Savaria, Y. (2013). Design of a C-element based clock domain crossing interface. Communication présentée à 24th International Conference on Microelectronics (ICM 2012), Algiers, Algeria (4 pages). Tiré de https://doi.org/10.1109/ICM.2012.6471395
      • Communication de conférence
        Hoque, K.A., Ait Mohamed, O., Savaria, Y. & Thibeault, C. (2013). Early analysis of soft error effects for aerospace applications using probabilistic model checking. Communication présentée à 2nd International Workshop of Formal Techniques for Safety-Critical Systems (FTSCS 2013), Queenstown, New Zealand (p. 54-70). Tiré de https://doi.org/10.1007/978-3-319-05416-2_5
      • Communication de conférence
        Bouanen, S., Thibeault, C., Savaria, Y. & Tremblay, J.P. (2013). Fault tolerant smart transducer interface for safety-critical avionics applications. Communication présentée à 32nd IEEE/AIAA Digital Avionics Systems Conference (DASC 2013), Syracuse, NY, USA.
      • Communication de conférence
        Hamad, G.B., Hasan, S.R., Mohamed, O.A. & Savaria, Y. (2013). Investigating the impact of input patterns, propagation paths, and re-convergent paths on the propagation induced pulse broadening. Communication présentée à Radiation Effects on Components and Systems (RADECS 2013), Oxford, UK.
      • Communication de conférence
        Hamad, G.B., Hasan, S.R., Mohamed, O.A. & Savaria, Y. (2013). Investigating the impact of propagation paths and re-convergent paths on the propagation induced pulse broadening. Communication présentée à 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS 2013), Oxford, United kingdom (p. 1-4). Tiré de https://doi.org/10.1109/RADECS.2013.6937387
      • Communication de conférence
        Stimpfling, T., Savaria, Y., Beliveau, A., Belanger, N. & Cherkaoui, O. (2013). Optimal packet classification applicable tothe OpenFlow context. Communication présentée à 1st ACM Workshop on High Performance and Programmable Networking (HPPN 2013), New York, NY, United states (p. 9-14).
      • Communication de conférence
        Guillemot, M., Blaquiere, Y. & Savaria, Y. (2013). Software Rendering Methods to Display Wafer Scale Integrated Circuit Dataset. Communication présentée à 26th Annual IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2013), Regina, Sask, CAN (p. 819-822).
    • 2012
      • Communication de conférence
        Nguyen, H.H., Guillemot, M., Savaria, Y. & Blaquiere, Y. (2012). A new approach for pin detection for an electronic system prototyping reconfigurable platform. Communication présentée à 23rd IEEE International Symposium on Rapid System Prototyping (RSP 2012), Piscataway, NJ, USA (p. 122-7).
      • Communication de conférence
        Pons, J.-F., Brault, J.-J. & Savaria, Y. (2012). An FPGA compatible asynchronous wake-up receiver for Wireless Sensor Networks. Communication présentée à 10th IEEE International New Circuits and Systems Conference (NEWCAS 2012), Montreal, QC, Canada (p. 373-376).
      • Communication de conférence
        Al-Bayati, Z., Ait Mohamed, O., Hasan, S.R. & Savaria, Y. (2012). A novel hybrid FIFO asynchronous clock domain crossing interfacing method. Communication présentée à 22nd Great Lakes Symposium on VLSI (GLSVLSI 2012), Salt Lake City, Utah (p. 271-274).
      • Communication de conférence
        Bany Hamad, G., Ait Mohamed, O., Rafay Hasan, S. & Savaria, Y. (2012). Identification of soft error glitch-propagation paths: Leveraging SAT solvers. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2012), Seoul, Korea, Republic of (p. 3258-3261).
      • Communication de conférence
        Nishi, R., Zhu, G. & Savaria, Y. (2012). Optimal scheduling policy for AFDX end-systems with virtual links of identical bandwidth allocation gap size. Communication présentée à 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2012), Montreal, QC, Canada.
      • Communication de conférence
        Al-Bayati, Z., Ait Mohamed, O., Savaria, Y. & Boukadoum, M. (2012). Probabilistic model checking of clock domain crossing interfaces. Communication présentée à 10th IEEE International New Circuits and Systems Conference (NEWCAS 2012), Montreal, QC, Canada (p. 193-196).
      • Communication de conférence
        Al-Terkawi Hasib, O., Andre, W., Blaquiere, Y. & Savaria, Y. (2012). Propagating analog signals through a fully digital network on an electronic system prototyping platform. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2012), Seoul, Korea, Republic of (p. 1983-1986).
      • Communication de conférence
        Pons, J.-F., Brault, J.-J. & Savaria, Y. (2012). State-holding free NULL Convention Logic. Communication présentée à 55th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2012), Boise, ID, United states (p. 322-325). Tiré de https://doi.org/10.1109/MWSCAS.2012.6292022
      • Communication de conférence
        Anane, A., Aboulhamid, E.M. & Savaria, Y. (2012). System modeling and multicore simulation using transactions. Communication présentée à International Conference on Embedded Computer Systems (SAMOS 2012), Samos, Grèce (p. 41-50).
      • Communication de conférence
        Allard, M., Grogan, P., Savaria, Y. & David, J.-P. (2012). Two-level configuration for FPGA: A new design methodology based on a computing fabric. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2012), Seoul, Korea, Republic of (p. 265-268).
    • 2011
      • Communication de conférence
        Zarrabi, H., Al-Khalili, A.J. & Savaria, Y. (2011). Activity management in battery-powered embedded systems: A case study of ZigBee&reg WSN. Communication présentée à 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon (p. 727-731).
      • Communication de conférence
        Kowarzyk, G., Belanger, N. & Savaria, Y. (2011). A GPGPU-based software implementation of the PBDI deinterlacing algorithm. Communication présentée à 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon (p. 780-783).
      • Communication de conférence
        Tawk, M., Zhu, G., Savaria, Y., Liu, X., Li, J. & Hu, F. (2011). A tight end-to-end delay bound and scheduling optimization of an avionics AFDX network. Communication présentée à 30th Digital Avionics Systems Conference (DASC 2011), Seattle, WA, United states (p. 7B31-7B310).
      • Communication de conférence
        Farah, R., Gan, Q., Langlois, J.M.P., Bilodeau, G.-A. & Savaria, Y. (2011). A tracking algorithm suitable for embedded systems implementation. Communication présentée à 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon (p. 256-259).
      • Communication de conférence
        Gil, D.C., Farah, R., Langlois, J.M.P., Bilodeau, G.-A. & Savaria, Y. (2011). Comparative analysis of contrast enhancement algorithms in surveillance imaging. Communication présentée à IEEE International Symposium of Circuits and Systems (ISCAS 2011), Rio de Janeiro, Brazil (p. 849-852).
      • Communication de conférence
        Vakili, S., Gil, D.C., Langlois, J.M.P., Savaria, Y. & Bois, G. (2011). Customized embedded processor design for global photographic tone mapping. Communication présentée à 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon (p. 382-385).
      • Communication de conférence
        Tawk, M., Zhu, G., Liu, X., Jian, L., Savaria, Y. & Hu, F. (2011). Optimal scheduling and delay analysis for AFDX end-systems. Communication présentée à SAE AeroTech Congress and Exhibition (AEROTECH 2011), Toulouse, France.
      • Communication de conférence
        Valorge, O., Andre, W., Savaria, Y. & Blaquieie, Y. (2011). Power supply analysis of a large area integrated circuit. Communication présentée à 9th IEEE International New Circuits and Systems Conference (NEWCAS 2011), Bordeaux, France (p. 398-401).
      • Communication de conférence
        Zarrabi, H., Al-Khalili, A. & Savaria, Y. (2011). Repeater insertion in power-managed VLSI systems. Communication présentée à 21st Great Lakes Symposium on VLSI (GLSVLSI 2011), Lausanne, Switzerland (p. 395-398).
      • Communication de conférence
        Bany Hamad, G., Mohamed, O.A., Hasan, S.R. & Savaria, Y. (2011). SEGP-finder: Tool for identification of soft error glitch-propagating paths at gate level. Communication présentée à 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon (p. 358-361). Tiré de https://doi.org/10.1109/ICECS.2011.6122287
    • 2010
      • Communication de conférence
        Zarrabi, H., Al-Khalili, A.J. & Savaria, Y. (2010). An interconnect-aware Dynamic Voltage Scaling scheme for DSM VLSI. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France (p. 41-44).
      • Communication de conférence
        Tanguay, L.-F., Savaria, Y. & Sawan, M. (2010). A 640 W frequency synthesizer dedicated to implantable medical microsystems in 90-nm CMOS. Communication présentée à 8th IEEE International NEWCAS Conference (NEWCAS 2010), Montreal, Quebec (p. 369-372).
      • Communication de conférence
        Hasib, O.A., Sawan, M. & Savaria, Y. (2010). Fully integrated ultra-low-power asynchronously driven step-down DC-DC converter. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France (p. 877-880).
      • Communication de conférence
        Berriah, O., Bougataya, M., Lakhssassi, A., Blaquiere, Y. & Savaria, Y. (2010). Thermal analysis of a miniature electronic power device matched to a silicon wafer. Communication présentée à 8th IEEE International NEWCAS Conference (NEWCAS 2010), Montreal, Quebec (p. 129-132).
    • 2009
      • Communication de conférence
        Ayachi, D., Savaria, Y. & Thibeault, C. (2009). A configurable platform for MPSoCs based on application specific instruction set processors. Communication présentée à Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France.
      • Communication de conférence
        Hashemi, S., Sawan, M. & Savaria, Y. (2009). A low-area power-efficient CMOS active rectifier for wirelessly powered medical devices. Communication présentée à 16th IEEE International Conference on Electronics, Circuits and Systems, Yasmine Hammamet, Tunisia (p. 635-638).
      • Communication de conférence
        Hasan, S.R., Pontikakis, B. & Savaria, Y. (2009). An all-digital skew-adaptive clock scheduling algorithm for heterogeneous multiprocessor systems on chips (MPSoCs). Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2009), Taipei, Taiwan (p. 2501-2504).
      • Communication de conférence
        Zarrabi, H., Al-Khalili, A.J. & Savaria, Y. (2009). An interconnect-aware delay model for dynamic voltage scaling in nm technologies. Communication présentée à 19th ACM Great Lakes Symposium on VLSI, Boston, MA, United states (p. 45-49).
      • Communication de conférence
        Lepercq, E., Valorege, O., Basile-Bellavance, Y., Laflamme-Mayer, N., Blaquière, Y. & Savaria, Y. (2009). An interconnection network for a novel reconfigurable circuit board. Communication présentée à 2nd Microsystems and Nanoelectronics Research Conference, Ottawa, Canada (p. 128-131).
      • Communication de conférence
        Zarreabi, H., Al-Khalili, A.J. & Savaria, Y. (2009). Estimation of energy performance in computing platforms. Communication présentée à 16th IEEE International Conference on Electronics, Circuits and Systems, Yasmine Hammamet, Tunisia (p. 783-786).
      • Communication de conférence
        Basile-Bellavance, Y., Blaquiere, Y. & Savaria, Y. (2009). Faults diagnosis methodology for the WaferNet interconnection network. Communication présentée à Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France.
      • Communication de conférence
        Hashemi, S., Sawan, M. & Savaria, Y. (2009). Fully-integrated low-voltage high-efficiency CMOS rectifier for wirelessly powered devices. Communication présentée à Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France.
      • Communication de conférence
        Bafumba-Lokilo, D., Savaria, Y. & David, J.-P. (2009). Generic array-based MPSoC architecture. Communication présentée à 2nd Microsystems and Nanoelectronics Research Conference, Ottawa, Canada (p. 128-131).
      • Communication de conférence
        Aubertin, P., Mohammadi, H.M., Savaria, Y. & Langlois, J.M.P. (2009). High performance ASIP implementation of PBDI: a new intra-field deinterlacing method. Communication présentée à Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France.
      • Communication de conférence
        Lepercq, E., Blaquiere, Y., Norman, R. & Savaria, Y. (2009). Workflow for an electronic configurable prototyping system. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2009), Taipei, Taiwan (p. 2005-2008).
    • 2008
      • Communication de conférence
        Nourivand, A., Al-Khalili, A.J. & Savaria, Y. (2008). Aggressive leakage reduction of SRAMs using error checking and correcting (ECC) techniques. Communication présentée à 51st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2008), Knoxville, TN, United states (p. 426-429).
      • Communication de conférence
        Lu, Z., El-Fouladi, J., Martel, S. & Savaria, Y. (2008). A hybrid bacteria and microparticle detection platform on a CMOS chip: design, simulation and testing considerations. Communication présentée à 14th IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW 2008).
      • Communication de conférence
        Hasan, S.R., Belanger, N. & Savaria, Y. (2008). All-digital skew-tolerant interfacing method for systems with rational frequency ratios among multiple clock domains: leveraging a priori timing information. Communication présentée à 1st Microsystems and Nanoelectronics Research Conference (p. 129-132).
      • Communication de conférence
        Norman, R., Valorge, O., Blaquiere, Y., Lepercq, E., Basile-Bellavance, Y., El-Alaoui, Y., Prytula, R. & Savaria, Y. (2008). An active reconfigurable circuit board. Communication présentée à Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008) (p. 351-354).
      • Communication de conférence
        Norman, R., Lepercq, E., Blaquiere, Y., Valorge, O., Basile-Bellavance, Y., Prytula, R. & Savaria, Y. (2008). An interconnection network for a novel reconfigurable circuit board. Communication présentée à Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008) (p. 129-132). Tiré de https://doi.org/10.1109/NEWCAS.2008.4606338
      • Communication de conférence
        Pontikakis, B., Bui, H.T., Boyer, F.-R. & Savaria, Y. (2008). A novel phase-locked loop (PLL) architecture without an analog loop filter for better integration in ultra-deep submicron SoCs. Communication présentée à Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008) (p. 363-366).
      • Communication de conférence
        Tanguay, L.F., Sawan, M. & Savaria, Y. (2008). A very-high output impedance current mirror for very-low voltage biomedical analog circuits. Communication présentée à IEEE Asia-Pacific Conference on Circuits and Systems, Macao, China (p. 642-645).
      • Communication de conférence
        Valorge, O., Nguyen, A.T., Blaquière, Y., Norman, R. & Savaria, Y. (2008). Digital signal propagation on a wafer-scale smart active programmable interconnect. Communication présentée à 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008), St. Julian's, Malta (p. 1059-1062).
      • Communication de conférence
        Bafumba-Lokilo, D., Savaria, Y. & David, J.-P. (2008). Generic crossbar network on chip for FPGA MPSoCs. Communication présentée à Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008) (p. 269-272).
      • Communication de conférence
        Basile-Bellavance, Y., Lepercq, E., Blaquiere, Y. & Savaria, Y. (2008). Hardware/software system co-verification of an active reconfigurable board with SystemC-VHDL. Communication présentée à 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008) (p. 1159-1162).
      • Communication de conférence
        Tremblay, J.-P., Savaria, Y., Thibeault, C. & Mbaye, M. (2008). Improving resource utilization in an multiple asynchronous ALU DSP architecture. Communication présentée à 1st Microsystems and Nanoelectronics Research Conference (p. 25-28).
      • Communication de conférence
        Ngoyi, G.-A.B., Langlois, J.M.P. & Savaria, Y. (2008). Iterative design method for video processors based on an architecture design language and its application to ELA deinterlacing. Communication présentée à Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008) (p. 37-40).
      • Communication de conférence
        Mbaye, M., Belanger, N., Savaria, Y. & Pierre, S. (2008). Loop-oriented metrics for exploring an application-specific architecture design-space. Communication présentée à International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2008) (p. 257-262).
      • Communication de conférence
        Anane, A., Aboulhamid, E.M., Vachon, J. & Savaria, Y. (2008). Modeling and simulation of complex heterogeneous systems. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2008), Seattle, WA, United states (p. 2873-2876).
      • Communication de conférence
        Sahraii, N., Savaria, Y., Thibeault, C. & Gagnon, F. (2008). Scheduling of turbo decoding on a multiprocessor platform to manage its processing effort variability. Communication présentée à Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008) (p. 73-76).
      • Communication de conférence
        Kowarzyk, G., Savaria, Y. & Haccoun, D. (2008). Searching for short-span convolutional doubly self-orthogonal codes: a parallel implicitly-exhaustive-search algorithm. Communication présentée à Canadian Conference on Electrical and Computer Engineering (CCECE 2008), Niagara Falls, Ontario (p. 001659-001662).
      • Communication de conférence
        Bougataya, M., Lakhsasi, A., Norman, R., Prytula, R., Blaquière, Y. & Savaria, Y. (2008). Steady state thermal analysis of a reconfigurable wafer-scale circuit board. Communication présentée à IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2008) (p. 411-415).
    • 2007
      • Communication de conférence
        Abderrahman, A., Savaria, Y., Khouas, A. & Sawan, M. (2007). Accurate testability analysis based-on multi-frequency test generation and a new testability metric. Communication présentée à IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Canada (p. 1356-1359).
      • Communication de conférence
        Naderi, A., Sawan, M. & Savaria, Y. (2007). A 1.8GHz CMOS continuous-time band-pass delta-sigma modulator for RF receivers. Communication présentée à 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007), Montréal, Canada (p. 1078-1081).
      • Communication de conférence
        Lu, Z., El-Fouladi, J., Savaria, Y. & Martel, S. (2007). A hybrid bacteria and microparticle detection platform on a CMOS chip. Communication présentée à 11th International Conference on Miniaturized Systems for Chemistry and Life Science, Paris, France.
      • Communication de conférence
        Pontikakis, B., Bui, H.T., Boyer, F.-R. & Savaria, Y. (2007). A low-complexity high-speed clock generator for dynamic frequency scaling of FPGA and standard-cell based designs. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, LA, United States (p. 633-636).
      • Communication de conférence
        El Fouladi, J., Lu, Z., Savaria, Y. & Martel, S. (2007). An integrated biosensor for the detection of bio-entities using magnetotactic bacteria and CMOS technology. Communication présentée à 29th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC 2007), Lyon, France (p. 119-122).
      • Communication de conférence
        Hashemi, S., Sawan, M. & Savaria, Y. (2007). A novel fully-integrated low-drop voltage cmos rectifier for wirelessly powered devices. Communication présentée à IEEE International Conference on Microelectronics, Cairo, Egypt (p. 333-336).
      • Communication de conférence
        Chebli, R., Sawan, M., Savaria, Y. & El-Sankary, K. (2007). High-voltage DMOS integrated circuits with floating gate protection technique. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, LA, United States (p. 3343-3346).
      • Communication de conférence
        Trabelisi, A., Boyer, F.R., Savaria, Y. & Boukadoum, M. (2007). Improving LPC Analysis of Speech in Additive Noise. Communication présentée à IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Canada (p. 93-96).
      • Communication de conférence
        Singh, R., Audet, Y., Gagnon, Y. & Savaria, Y. (2007). Integrated circuit trimming technique for offset reduction in a precision CMOS amplifier. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, LA, United States (p. 709-712).
      • Communication de conférence
        Trabelisi, A., Boyer, F.R., Savaria, Y. & Boukadoum, M. (2007). Iterative Noise-Compensated Method to Improve LPC Based Speech Analysis. Communication présentée à 14h IEEE International Conference on Electronics, Circuits & Systems, Marrakech, Morocco (p. 1364-1367).
      • Communication de conférence
        Binet, V., Savaria, Y., Meunier, M. & Gagnon, Y. (2007). Modeling the substrate noise injected by a DC-DC converter. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, LA, United States (p. 309-312).
      • Communication de conférence
        Abderrahman, A., Savaria, Y., Khouas, A. & Sawan, M. (2007). New Analog Test Metrics Based on Probabilistic and Deterministic Combination Approaches. Communication présentée à 14th IEEE International Conference on Electronics, Circuits and Systems, Marrakech, Morocco (p. 82-85).
      • Communication de conférence
        Pontikakis, B., Boyer, F.-R., Savaria, Y. & Bui, H.T. (2007). Precise free-running period synthesizer (FRPS) with process and temperature compensation. Communication présentée à 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007) (p. 1118-1121).
      • Communication de conférence
        Meunier, M., Gagnon, Y., Lacourse, A., Ducharme, M., Rioux, S. & Savaria, Y. (2007). Precision resistor laser trimming for analog microelectronics. Communication présentée à Photonic Applications Systems Technologies Conference, Baltimore, Maryland, USA.
      • Communication de conférence
        Valorge, O., Marche, D., Lacourse, A., Sawan, M. & Savaria, Y. (2007). Signal Integrity Analysis of a High Precision D/A Converter. Communication présentée à 14th IEEE International Conference on Electronics, Circuits and Systems, Marrakech, Morocco (p. 1224-1227).
      • Communication de conférence
        Trabelsi, A., Boyer, F.R. & Savaria, Y. (2007). Speech enhancement based noise PSD estimator to remove cosine shaped residual noise. Communication présentée à 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007) (p. 393-396).
    • 2006
      • Communication de conférence
        Naderi, A., Sawan, M. & Savaria, Y. (2006). A novel 2-GHz band-pass delta modulator dedicated to wireless receivers. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece.
      • Communication de conférence
        Hashemi, S., Sawan, M. & Savaria, Y. (2006). A power planning model for implantable stimulators. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece.
      • Communication de conférence
        Castonguay, A. & Savaria, Y. (2006). Architecture of a hypertransport tunnel. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece.
      • Communication de conférence
        Mohammadi, H.M., Langlois, J.M.P. & Savaria, Y. (2006). A threshold-based deinterlacing algorithm using motion compensation and directional interpolation. Communication présentée à 13th IEEE International Conference on Electronics, Circuits and Systems, Nice, France (p. 459-462).
      • Communication de conférence
        Mahvash Mohammadi, H., Langlois, J.M.P. & Savaria, Y. (2006). A threshold-based de-interlacing algorithm using motion compension and directional interpolation. Communication présentée à IEEE International Conference on Electronics, Circuits and Systems (ICECS 2006), Nice, Cote d'Azur.
      • Communication de conférence
        Pontikakis, B., Boyer, F.-R. & Savaria, Y. (2006). A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece (p. 1259-1262).
      • Communication de conférence
        Chureau, A., Savaria, Y., Boland, J.-F., Zilic, Z., Thibeault, C. & Gagnon, F. (2006). Building heterogeneous functional prototypes using articulated interfaces. Communication présentée à 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada.
      • Communication de conférence
        Mbaye, M., Lebel, D., Belanger, N., Savaria, Y. & Pierre, S. (2006). Design exploration with an application-specific instruction-set processor for ELA deinterlacing. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece.
      • Communication de conférence
        Naderi, A., Sawan, M. & Savaria, Y. (2006). Design of an active-RC bandpass filter for a subsampling RF delta modulator. Communication présentée à Canadian Conference on Electrical and Computer Engineering (CCECE 2006), Ottawa, Ontario (p. 967-970).
      • Communication de conférence
        Bui, H.T. & Savaria, Y. (2006). High speed differential pulse-width control loop based on frequency-to-voltage converters. Communication présentée à 16th ACM Great Lakes Symposium on VLSI (GLSVLSI 2006), Philadelphia, USA.
      • Communication de conférence
        Huang, Z., Savaria, Y., Sawan, M. & Meinga, R. (2006). High-voltage operational amplifier based on dual floating-gate transistors. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece.
      • Communication de conférence
        Belanger, N. & Savaria, Y. (2006). On the design of a double precision logarithmic number system arithmetic unit. Communication présentée à 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada.
      • Communication de conférence
        Mahvash, M., H., Savaria, Y. & Langlois, J.M.P. (2006). Real-time ELA de-interlacing with the Xtensa reconfigurable processor. Communication présentée à 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada (p. 25-28).
      • Communication de conférence
        Deslauriers, F., Langevin, M., Bois, G., Savaria, Y. & Paulin, P. (2006). RoC: a scalable network on chip based on the token ring concept. Communication présentée à 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada.
      • Communication de conférence
        Ignat, N., Nicolescu, B., Savaria, Y. & Nicolescu, G. (2006). Soft-Error Classification and Impact Analysis on Real-Time Operating Systems. Communication présentée à Design, Automation and Test in Europe Conference and Exhibition (DATE 2006) (p. 180-185).
      • Communication de conférence
        El fouladi, J., André, W., Savaria, Y. & Martel, S. (2006). System design of an integrated measurement electronic subsystem for bacteria detection using and electrode array and MC-1 magnetotactic bacteria. Communication présentée à International Workshop on Computer Architecture for Machine Perception and Sensing (CAMP 2006), Montréal, Canada (p. 38-41).
    • 2005
      • Communication de conférence
        Salomon, M.E., Khouas, A. & Savaria, Y. (2005). A Complete Spurs Distribution Model for Direct Digital Period Synthesizers. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan (p. 4859-4862).
      • Communication de conférence
        Dubois, M., Savaria, Y. & Bois, G. (2005). A Generic Ahb Bus for Implementing High-Speed Locally Synchronous Islands. Communication présentée à IEEE SoutheastCon 2004, Fort Lauderdale, Florida, USA (p. 11-16).
      • Communication de conférence
        Bui, H.T. & Savaria, Y. (2005). A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in Socs. Communication présentée à 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005), Banff, Alberta, Canada (p. 557-562).
      • Communication de conférence
        Castonguay, A. & Savaria, Y. (2005). A Hypertransport Chip-to-Chip Interconnect Tunnel Developed Using Systemc. Communication présentée à 16th International Workshop on Rapid System Prototyping, Montréal, Canada (p. 264-266).
      • Communication de conférence
        Morin, D., Savaria, Y. & Sawan, M. (2005). A 200 MSPS 10-bit pipelined ADC using digital calibration. Communication présentée à 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Quebec City, Que., Canada (p. 67-70).
      • Communication de conférence
        Naderi, A.H., Sawan, M. & Savaria, Y. (2005). A 1-mW 2-GHz Q-enhanced LC bandpass filter for low-power RF applications. Communication présentée à 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005) (p. 365-368).
      • Communication de conférence
        Ling, W. & Savaria, Y. (2005). Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations. Communication présentée à 6th International Symposium on Quality Electronic Design, San Jose, California (p. 688-693).
      • Communication de conférence
        Marche, D., Savaria, Y. & Gagnon, Y. (2005). A New Switch Compensation Technique for Inverted R-2r Ladder Dacs. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan (p. 196-199).
      • Communication de conférence
        Dang, H., Sawan, M. & Savaria, Y. (2005). A Novel Approach for Implementing Ultra-High Speed Flash Adc Using Mcml Circuits. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan (p. 6158-6161).
      • Communication de conférence
        Landry, A., Nekili, M. & Savaria, Y. (2005). A novel 2 GHz Mulit-layer AMBA high-Speed bus interconnect matrix for SoC platforms. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2005), Japon (p. 3343-3346).
      • Communication de conférence
        Mbaye, M., Bélanger, N., Savaria, Y. & Pierre, S. (2005). Application Specific Instruction-Set Processor Generation for Video Processing Based on Loop Optimization. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan (p. 3515-3518).
      • Communication de conférence
        Chebli, R., Sawan, M. & Savaria, Y. (2005). A programmable posititve and negative high-voltage DC-DC converter dedicated for ultrasonic applications. Communication présentée à 48th Midwest Symposium on Circuits and Systems (MWSCAS 2005), Cincinnati, Ohio (p. 679-682).
      • Communication de conférence
        Wild, G., Savaria, Y. & Meunier, M. (2005). Characterization of Laser-Induced Photoexcitation Effect on a Surrounding CMOS Ring Oscillator. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan (p. 3696-3699).
      • Communication de conférence
        Landry, A., Savaria, Y. & Nekili, M. (2005). Circuits techniques for a 2 GHz AMBA AHB Bus. Communication présentée à 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Québec, Canada (p. 311-314).
      • Communication de conférence
        Grou-Szabo, R., Ghattas, H., Savaria, Y. & Nicolescu, G. (2005). Component-Based Methodology for Hardware Design of a Dataflow Processing Network. Communication présentée à 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005), Banff, Alberta, Canada (p. 289-294).
      • Communication de conférence
        Deca, R., Mahrez, O., Cherkaoui, O., Savaria, Y. & Slone, D. (2005). Contributions to automated testing of network service interactions. Communication présentée à 5e Colloque International sur les nouvelles technologies de la répartition (NOTERE 2005), Gatineau, Québec (p. 175-180).
      • Communication de conférence
        Bui, H.T. & Savaria, Y. (2005). Design and analysis of XOR gates for high-speed and low-jitter applications. Communication présentée à 9th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI 2005), Orlando, Floride (p. 60-65).
      • Communication de conférence
        Rioux, S., Lacourse, A., Ducharme, M., Gagnon, Y., Savaria, Y. & Meunier, M. (2005). Design methods for CMOS low-current finely tunable voltage references covering a wide output range. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2005), Japon (p. 4257-4260).
      • Communication de conférence
        Provost, G., Cantin, M.A., Sawan, M., C., C., Savaria, Y. & Haccoun, D. (2005). Fast parameters optimization of an iterative decoder using a configurable hardware accelerator. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japon (p. 4159-4162).
      • Communication de conférence
        Chebli, R., Sawan, M. & Savaria, Y. (2005). Gate oxide protection in HV CMOS/DMOS integrated circuits: Design and experimental results. Communication présentée à IEEE International Conference on Electronics, Circuits and Systems (ICECS 2005), Tunisie.
      • Communication de conférence
        Sawan, M., Djemouai, A., El-Sankary, K., Dang, H., Naderi, A., Savaria, Y. & Gagnon, F. (2005). High speed ADCs dedicated for wideband wireless receivers. Communication présentée à 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005) (p. 283-286).
      • Communication de conférence
        Bui, H.T. & Savaria, Y. (2005). High-speed differential frequency-to-voltage converter. Communication présentée à 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005) (p. 373-376).
      • Communication de conférence
        Epassa, H.G., Boyer, F.R. & Savaria, Y. (2005). Implementation of a Cycle by Cycle Variable Speed Processor. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan (p. 3335-3338).
      • Communication de conférence
        Hashemi, S., Sawan, M. & Savaria, Y. (2005). Modeling power budget requirements of implantable electronic devices. Communication présentée à IEEE International Conference on Electronics, Circuits and Systems (ICECS 2005), Tunisie.
      • Communication de conférence
        Mahoney, P., Savaria, Y., Bois, G. & Plante, P. (2005). Parallel hashing memories : an alternative to content addressable memories. Communication présentée à 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Quebec City, Que., Canada (p. 223-226).
      • Communication de conférence
        Catudal, S., Cantin, M.A. & Savaria, Y. (2005). Parameters Estimation Applied to Automatic Video Processing Algorithms Validation. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan (p. 3439-3442).
      • Communication de conférence
        Pontikakis, B., Boyer, F.R. & Savaria, Y. (2005). Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period. Communication présentée à 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005), Banff, Alberta, Canada (p. 454-458).
      • Communication de conférence
        Nicolescu, B., Ignat, N., Savaria, Y. & Nicolescu, G. (2005). Sensitivity of real-time operating systems to transient faults : A cause study for microC kernel. Communication présentée à 8th European Conference on Radiation and its Effects on Components and Systems (RADECS 2005).
      • Communication de conférence
        Saheb, J.F., Richard, J.-F., Meingan, R., Sawan, M. & Savaria, Y. (2005). System integration of high voltage electrostatic MEMS Actuators. Communication présentée à 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Québec, Canada (p. 155-158).
      • Communication de conférence
        Chureau, A., Savaria, Y. & Aboulhamid, E.M. (2005). The Role of Model-Level Transactors and Uml in Functional Prototyping of Systems-on-Chip: a Software-Radio Application. Communication présentée à Design, Automation and Test in Europe Conference and Exhibition (DATE 2005), Munich, Germany (p. 698-703).
    • 2004
      • Communication de conférence
        Landry, A., Savaria, Y. & Nekili, M. (2004). A beyond-1 GHz high-speed bus for SoC DSP platforms. Communication présentée à 16th International Conference on Microelectronics (ICM 2004), Tunisie (p. 46-49).
      • Communication de conférence
        Tanguay, B., Savaria, Y. & Sawan, M. (2004). Accelerating equalization algorithms using the Xtensa configurable processor. Communication présentée à 16th International Conference on Microelectronics (ICM 2004), Tunisie (p. 434-437).
      • Communication de conférence
        Nsame, P. & Savaria, Y. (2004). A customizable embedded SoC platform architecture. Communication présentée à 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada (p. 299-304).
      • Communication de conférence
        Zhengrong, H., Savaria, Y. & Sawan, M. (2004). A dynamically controlled and refreshed low-power level-up shifter. Communication présentée à 47th Midwest Symposium on Circuits and Systems (MWSCAS 2004), Hiroshima, Japon (p. 97-100).
      • Communication de conférence
        Lafrance, L.-P. & Savaria, Y. (2004). A framework for implementing reusable digital signal processing modules. Communication présentée à 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada (p. 51-4).
      • Communication de conférence
        Tohio, B., Pierre, S., Savaria, Y. & Mbaye, M.M. (2004). Algorithm and criteria to assess protocol convertibility in network processing environments. Communication présentée à WSEAS International Conference on Telecommunications and Informatics (TELE-INFO 2004), Cancun, Mexique.
      • Communication de conférence
        Calbaza, D.E., Cordos, I., Seth-Smith, N. & Savaria, Y. (2004). An Adpll Circuit Using a Ddps for Genlock Applications. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2004) (p. 569-572).
      • Communication de conférence
        Jin, Z.-F., Yang, M., Savaria, Y. & Wu, K. (2004). Analysis of gate modulation in nanoscale field effect transistors using an equivalent substrate integrated waveguide (SIW) model. Communication présentée à 10th International Symposium on Antenna Technology and Applied Electromagnetics and URSI Conference (ANTEM/URSI 2004), Ottawa, Ont., Canada (p. 63-65). Tiré de https://doi.org/10.1109/ANTEM.2004.7860633
      • Communication de conférence
        Robert, M., Savaria, Y. & Wang, C. (2004). Analysis of metrics used to compare analog-to-digital converters. Communication présentée à 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal (p. 301-304).
      • Communication de conférence
        Boland, J.F., Chureau, A., Thibeault, C., Savaria, Y., Gagnon, F. & Zilic, Z. (2004). An efficient methodology for design and verification of an equalizer for a software defined radio. Communication présentée à 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal (p. 73-76).
      • Communication de conférence
        Duval, O., Lafrance, L.P., Savaria, Y. & Desjardins, R. (2004). An Integrated Test Platform for Nanostructure Electrical Characterization. Communication présentée à International Conference on Mems, Nano and Smart Systems (ICMENS 2004), Banff, Canada (p. 237-242).
      • Communication de conférence
        Morin, D., Normandin, F., Grandmaison, M.E., Dang, H., Savaria, Y. & Sawan, M. (2004). An intellectual property module for auto-calibration of time-interleaved pipelined analog-to-digital converters. Communication présentée à 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada (p. 111-114).
      • Communication de conférence
        Duval, O. & Savaria, Y. (2004). An on-chip delay measurements module for nanostructures characterization. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2004), Vancouver, BC, Canada (p. 721-724).
      • Communication de conférence
        Peterson, K. & Savaria, Y. (2004). Assertion-based on-line verification and debug environment for complex hardware systems. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2004), Vancouver, BC, Canada (p. 685-688).
      • Communication de conférence
        Boyer, F.-R., Epassa, H.G., Pontikakis, B., Savaria, Y. & Ling, W. (2004). A variable period clock synthesis (VPCS) architecture for next-generation power-aware SoC applications. Communication présentée à 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal (p. 145-148).
      • Communication de conférence
        Hashemi, S., Sawan, M. & Savaria, Y. (2004). Characterization of Stress Induced Defects in Deep Sub-Micron MOSFETS. Communication présentée à 2nd Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montreal, Que., Canada (p. 329-332).
      • Communication de conférence
        Gorse, N., Aboulhamid, E.M. & Savaria, Y. (2004). Consistency validation of high-level requirements. Communication présentée à 4th International Workshop on System on Chip for Real Time Applications (IWSOC 2004), Banff (p. 93-98).
      • Communication de conférence
        Hasan, S.R., Landry, A., Savaria, Y. & Nekili, M. (2004). Design constraints of hypertransport-compatible networks-on-chip. Communication présentée à 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal (p. 269-272).
      • Communication de conférence
        Gorse, N., Metzger, M., Lapalme, J., Aboulhamid, E.M., Savaria, y. & Nicolescu, G. (2004). Enhancing ESys.Net with a semi-formal verification layer. Communication présentée à 16th International Conference on Microelectronics (ICM 2004), Tunisie (p. 388-391).
      • Communication de conférence
        Bui, H.T. & Savaria, Y. (2004). 10 GHz PLL using active shunt-peaked MCML gates and improved frequency acquisition XOR phase detector in 0.18 mu m CMOS. Communication présentée à 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada (p. 115-118).
      • Communication de conférence
        Richard, J.-F. & Savaria, Y. (2004). High voltage charge pump using standard CMOS technology. Communication présentée à 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal (p. 317-320).
      • Communication de conférence
        Chureau, A., Savaria, Y. & Aboulhamid, E.M. (2004). Interface-based design of systems-on-chip using UML-RT. Communication présentée à 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada (p. 39-44).
      • Communication de conférence
        Gorse, N., Bélanger, P., Aboulhamid, E.M. & Savaria, Y. (2004). Mixing linguistic and formal techniques for high-level requirements engineering. Communication présentée à 16th International Conference on Microelectronics (ICM 2004), Tunisie (p. 339-342).
      • Communication de conférence
        Nsame, P. & Savaria, Y. (2004). Multi-processor SoC integration: a case study on BlueGene. Communication présentée à IEEE International SOC Conference (SOCC 2004) (p. 201-204).
      • Communication de conférence
        Granger, E., Catudal, S., Grou, R., Mbaye, M.M. & Savaria, Y. (2004). On current strategies for hardware acceleration of digital image restoration filters. Communication présentée à 4th WSEAS International Conference on Signal, Speech and Image Processing (ICOSSIP 2004), Izmir, Turquie.
      • Communication de conférence
        Dubois, M., Savaria, Y. & Haccoun, D. (2004). On low power shift register hardware realizations for convolutional encoders and decoders. Communication présentée à 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montreal, Que., Canada (p. 213-216).
      • Communication de conférence
        Nicolescu, B., Savaria, Y. & Velazco, R. (2004). Performance evaluation and failure rate prediction for the soft implemented error detection technique. Communication présentée à 10th IEEE International On-Line Testing Symposium, Funchal, Madeira Island, Portugal (p. 233-238).
      • Communication de conférence
        Tohio, B., Pierre, S., Savaria, Y. & Mbaye, m.M.M. (2004). Protocol convertibility in network processing environments. Communication présentée à 6th WSEAS International Conference on Telecommunications and Informatics (TELE-INFO 2004), Cancun, Mexico (p. 1).
      • Communication de conférence
        Huang, Z., Savaria, Y. & Sawan, M. (2004). Robust design of a dynamically controlled low-power level-up shifter operating up to 300V. Communication présentée à 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal (p. 321-324).
      • Communication de conférence
        Bui, H.T. & Savaria, Y. (2004). Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2004), Vancouver, BC, Canada (p. 369-372).
      • Communication de conférence
        Bui, T. & Savaria, Y. (2004). Shunt-peaking of MCML gates using active inductors. Communication présentée à 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal (p. 361-364).
      • Communication de conférence
        Izouggaghen, B., Khouas, A. & Savaria, Y. (2004). Spurs modeling in direct digital period synthesizers related to phase accumulator truncation. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2004), Vancouver, BC, Canada (p. 389-392).
      • Communication de conférence
        Layachi, M., Savaria, Y. & Rochefort, A. (2004). The Effect of Pi-Coupling on the Electronic Properties of 1,4-Dithiol Benzene Stacking. Communication présentée à International Conference on Mems, Nano and Smart Systems (ICMENS 2004) (p. 588-592).
      • Communication de conférence
        Bougataya, M., Lakhasasi, A., Savaria, Y. & Massicotte, D. (2004). Thermo-mechanical stress analysis of VLSI devices by partially coupled finite element method. Communication présentée à 18th Annual Canadian Conference on Electrical and Computer Engineering (CCEC 2004), Niagara Falls, Ontario (p. 509-513).
      • Communication de conférence
        Nicolescu, B., Gorse, N., Savaria, Y., Aboulhamid, E.M. & Velazco, R. (2004). Validating a dynamic signature monitoring approach using the LTL mocel checking technique. Communication présentée à Workshop on Radiation Effects on Components and Systems (RADECS 2004), Madrid, Espagne (p. 93-96).
      • Communication de conférence
        Ling, W. & Savaria, Y. (2004). Variable-precision multiplier for equalizer with adaptive modulation. Communication présentée à 47th Midwest Symposium on Circuits and Systems (MWSCAS 2004), Hiroshima, Japon (p. 553-556).
      • Communication de conférence
        Regimbal, S., Savaria, Y. & Bois, G. (2004). Verification strategy determination using dependence analysis of transaction-level models. Communication présentée à 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada (p. 87-92).
    • 2003
      • Communication de conférence
        Renaud, M. & Savaria, Y. (2003). A CMOS three-state frequency detector complementary to an enhanced linear phase detector for PLL, DLL or high frequency clock skew measurement. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2003) (p. 148-151).
      • Communication de conférence
        Regimbal, S., Lemire, J.F., Savaria, Y., Bois, G., Aboulhamid, M. & Baron, A. (2003). Aspect Partitioning for Hardware Verification Reuse. Communication présentée à System-on-Chip for Real-Time Applications (p. 51-60).
      • Communication de conférence
        Trabelsi, A., Savaria, Y. & Audet, Y. (2003). Automatic offset correction technique based on active load tuning. Communication présentée à 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), Montréal, Canada (p. 5-8).
      • Communication de conférence
        Regimbal, S., Lemire, J.-F., Savaria, Y., Bois, G., Aboulhamid, E.M. & Baron, A. (2003). Automating functional coverage analysis based on an executable specification. Communication présentée à 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (p. 228-234).
      • Communication de conférence
        Jin, Z.F., Laurin, J.J. & Savaria, Y. (2003). Comparison of Propagation Characteristics Between Single and Coupled Mis Interconnect Topologies in Vlsi Circuits. Communication présentée à Canadian Conference on Electrical and Computer Engineering (CCECE 2003) (p. 5-8).
      • Communication de conférence
        Bissou, J.P. & Savaria, Y. (2003). Conception de haut niveau d'une plate-forme SOC pour la conversion de protocoles réseaux. Communication présentée à Canadian Conference on Electrical and Computer Engineering (CCECE 2003) (p. 1271-1274).
      • Communication de conférence
        Ghattas, H. & Savaria, Y. (2003). Design of dedicated low complexity embedded processors for SOC network processing applications. Communication présentée à 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), Montréal, Canada (p. 21-24).
      • Communication de conférence
        Nicolescu, B., Perronnard, P., Velazco, R. & Savaria, Y. (2003). Efficiency of transient bit-flips detection by software means a complete study. Communication présentée à 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2003), Cambridge, MA, USA (p. 377-384). Tiré de https://doi.org/10.1109/DFTVS.2003.1250134
      • Communication de conférence
        Boudjella, A., Jin, Z.F. & Savaria, Y. (2003). Electrical field analysis of nanoscaled field effect transistors. Communication présentée à International Microprocesses and Nanotechnology Conference, Tokyo, japon (p. 240-241).
      • Communication de conférence
        Khali, H. & Savaria, Y. (2003). Hardware-software co design model for real-time 3D image computation using active laser range finders : a case study. Communication présentée à 10th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2003), Sharjah, United Arab Emirates (p. 854-857). Tiré de https://doi.org/10.1109/ICECS.2003.1301921
      • Communication de conférence
        Pepga bissou, J., Dubois, M., Savaria, Y. & Bois, G. (2003). High speed system bus for a SoC network processing platform. Communication présentée à 15th International Conference on Microelectronics (ICM 2003), Le Caire, Égypte (p. 194-197).
      • Communication de conférence
        Bissou, J.P., Dubois, M., Savaria, Y. & Bois, G. (2003). High-speed system bus for a SoC network processing platform. Communication présentée à 15th International Conference on Microelectronics (ICM 2003), Cairo, Egypt (p. 194-197). Tiré de https://doi.org/10.1109/ICM.2003.238564
      • Communication de conférence
        Richard, J.F., Lessard, B., Meingan, R., Martel, S. & Savaria, Y. (2003). High voltage interfaces for CMOS/DMOS technologies. Communication présentée à 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), Montréal, Canada (p. 93-96).
      • Communication de conférence
        Lu, M., Savaria, Y., Qiu, B. & Taillefer, J. (2003). IEEE 1149.1 based defect and fault tolerant scan chain for wafer scale integration. Communication présentée à 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2003), Boston, MA, United states (p. 18-25). Tiré de https://doi.org/10.1109/DFTVS.2003.1250091
      • Communication de conférence
        Lu, M., Savaria, Y., Qiu, B. & Taillefer, J. (2003). IEEE 1149.1 based defect and fault tolerant scan chain for water safe integration. Communication présentée à DFT 2003, Boston, USA (p. 18-25).
      • Communication de conférence
        Lemire, J.F., Aboulhamid, E.M., Savaria, Y., Bois, G. & Baron, A. (2003). Implementing e assertion checkers from an SDL executable specifications. Communication présentée à DVCON, San José, USA.
      • Communication de conférence
        Loiseau, L. & Savaria, Y. (2003). Methodologies and Strategies for Effective Design-Reuse. Communication présentée à System-on-Chip for Real-Time Applications (p. 31-40).
      • Communication de conférence
        Tang, Y., Qian, L., Wang, Y. & Savaria, Y. (2003). New memory reference reduction method for FFT implementation on DSP. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2003), Bangkok, Thailand (p. 111-116).
      • Communication de conférence
        Mbaye, M.M., Tohio, B., Savaria, Y. & Pierre, S. (2003). Performance of a Firewire-Ethernet Protocols Conversion on an Arm7 Embedded Processor. Communication présentée à Canadian Conference on Electrical and Computer Engineering (CCECE 2003) (p. 1267-1270).
      • Communication de conférence
        Tohio, B., Pierre, S., Savaria, Y. & Mbaye, M.M. (2003). Protocol Convertibility in a Network Processing Environment. Communication présentée à Canadian Conference on Electrical and Computer Engineering (CCECE 2003) (p. 801-804). Tiré de https://doi.org/10.1109/CCECE.2003.1226016
      • Communication de conférence
        Nicolescu, B., Savaria, Y. & Velazco, R. (2003). SIED: software implemented error detection. Communication présentée à 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2003), Boston, MA, United states (p. 589-596). Tiré de https://doi.org/10.1109/DFTVS.2003.1250159
      • Communication de conférence
        Ghattas, H., Mbaye, M.M., Pepga, J.B. & Savaria, Y. (2003). SoC platform architecture for a network processor. Communication présentée à International Symposium on System-on-Chip, Tampere, Finland (p. 49-52).
      • Communication de conférence
        Bougataya, M., Lakhsasi, A., Savaria, Y. & Massicotte, D. (2003). Stress and distortion behavior for VLSI steady state thermal analysis. Communication présentée à Canadian Conference on Electrical and Computer Engineering (CCECE 2003) (p. 111-116).
      • Communication de conférence
        Nsame, P. & Savaria, Y. (2003). System-level design closure. Communication présentée à 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), Montréal, Canada (p. 101-104).
      • Communication de conférence
        Chabini, N., Chabini, I., Aboulhamid, E.M. & Savaria, Y. (2003). Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs. Communication présentée à Great Lakes Symposium on VLSI (GLSVLSI 2003), Washington, D. C., USA (p. 221-224).
      • Communication de conférence
        Lamarche, P.H. & Savaria, Y. (2003). VHDL source code generator and analysis tool to design linear interpolars. Communication présentée à 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), Montréal, Canada (p. 69-72).
    • 2002
      • Communication de conférence
        Fouzar, Y., Savaria, Y. & Sawan, M. (2002). A CMOS phase-locked loop with an auto-calibrated VCO. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2002) (p. 177-180).
      • Communication de conférence
        Cantin, M.-A., Savaria, Y. & Lavoie, P. (2002). A comparison of automatic word length optimization procedures. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2002) (p. 612-615).
      • Communication de conférence
        Dido, J., Geraudie, N., Loiseau, L., Payeur, O., Savaria, Y. & Poirier, D. (2002). A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs. Communication présentée à 10th ACM International Symposium on Field-Programmable Gate Arrays (FPGA 2002) (p. 50-55).
      • Communication de conférence
        Renaud, M. & Savaria, Y. (2002). A linear phase detector for arbitrary clock signals. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2002) (p. 775-778).
      • Communication de conférence
        Hashemi, S., Sawan, M. & Savaria, Y. (2002). Analysis of power chains in transcutaneously powered electronic implants. Communication présentée à 7th Annual Conference of the International Functional Electrical Stimulation Society (IFESS 2002), Lubljana (p. 196-198).
      • Communication de conférence
        Lafrance, L.-P., Cantin, M.-A., Savaria, Y., Sung, S.H. & Lavoie, P. (2002). Architecture and performance characterization of hardware and software implementations of the Crozier frequency estimation algorithm. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2002) (p. 823-826).
      • Communication de conférence
        Meunier, M., Gagnon, Y., Savaria, Y. & Lacourse, A. (2002). Laser tuning silicon microdevices for analogue microelectronics. Communication présentée à SPIE Regional Meeting on Optoelectronics, Photonics, and Imaging (Opto Canada 2002), Ottawa, Ont., Can. (p. 205-208).
      • Communication de conférence
        Bendali, A. & Savaria, Y. (2002). Low-voltage bandgap reference with temperature compensation based on a threshold voltage technique. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2002) (p. 201-204).
      • Communication de conférence
        Chabini, N., Aboulhamid, E.M., Chabini, I. & Savaria, Y. (2002). Minimizing the Number of Phases in Clocked Digital Designs Derived Using Modulo Scheduling Techniques. Communication présentée à 14th International Conference on Microelectronics (ICM 2002) (p. 92-95).
    • 2001
      • Communication de conférence
        Cantin, M.-A., Savaria, Y., Prodanos, D. & Lavoie, P. (2001). An automatic word length determination method. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2001), Sydney, NSW, Australia (p. 53-56).
      • Communication de conférence
        Fouzar, Y., Savaria, Y. & Sawan, M. (2001). A new controlled gain phase-locked loop technique. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2001), Sydney, NSW, Australia (p. 810-813).
      • Communication de conférence
        Meunier, M., Gagnon, Y., Savaria, Y., Lacourse, A. & Cadotte, M. (2001). A novel laser trimming technique for microelectronics. Communication présentée à 6th Conference on Laser Applications in Microelectronic and Optoelectronic Manufacturing (LAMOM 2001) (p. 385-392).
      • Communication de conférence
        Chabini, N., Aboulhamid, M. & Savaria, Y. (2001). Determining schedules for reducing power consuption using mulyiple supply voltages. Communication présentée à International Conference on Computer Design (ICCD 2001), Austin, Texas (p. 546-552).
      • Communication de conférence
        Chabini, N., Aboulhamid, M. & Savaria, Y. (2001). Efficient methods for reducing register and phase requirements for synchronous circuits derived using software pipeling techniques. Communication présentée à European Conference on Circuit Theory and Design, Espoo, Finland (p. 237-240).
      • Communication de conférence
        Chabini, N., Aboulhamid, E.M. & Savaria, Y. (2001). Fast method for determining an efficient bound on the optimal solution of the cost-to-time ratio problem. Communication présentée à 5th World Multiconference on Systemics, Cybernetics and Informatics (SCI 2001) and 7th International Conference in Information Systems Analysis and Synthesis (ISAS 2001), Orlando, Floride (p. 195-200).
      • Communication de conférence
        Chabini, N. & Savaria, Y. (2001). Methods for optimizating register placement in synchronous circuits derived using software pipelining techniques. Communication présentée à 14th International Symposium on System Synthesis (ISSS 2001), Montréal , Québec (p. 209-214).
      • Communication de conférence
        Nekili, M., Savaria, Y. & Bois, G. (2001). Minimizing process-induced skew using elay tuning. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2001), Sydney, Australie (p. 426-429).
      • Communication de conférence
        Chabini, N., Aboulhamid, E.M. & Savaria, Y. (2001). Minimizing registe requirements for synchronous circuits derived using software pipelining techniques. Communication présentée à 13th International Conference on Microelectronics (ICM 2001), Rabat, Maroc (p. 249-252).
      • Communication de conférence
        Thériault, L., Audet, D. & Savaria, Y. (2001). Performance estimators for hardware/software co-design. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2001), Sydney, Australie (p. 17-20).
      • Communication de conférence
        Chabini, N., Aboulhamid, E.M. & Savaria, Y. (2001). Reducing register and phase requirements for synchronous circuits derived using software pipeling techniques. Communication présentée à IEEE Computer Society Workshop on VLSI (WVLSI 2001), Orlando, Floride (p. 71-77).
      • Communication de conférence
        Chabini, N., Aboulhamid, E.M. & Savaria, Y. (2001). Reducing register and phase requirements for synchronous circuits derived using software pipelining techniques. Communication présentée à IEEE Computer Society Workshop on VLSI (WVLSI 2001), Orlando, FL, United states (p. 71-77). Tiré de https://doi.org/10.1109/IWV.2001.923142
      • Communication de conférence
        Monte, G., Antaki, B., Patenaude, S., Savaria, Y., Thibeault, C. & Trouborst, P. (2001). Tools for the characterization of bipolar CML testability. Communication présentée à 19th IEEE VLSI Test Symposium (VTS 2001), Marina Del Rey, CA, USA (p. 388-395).
    • 2000
      • Communication de conférence
        Calbaza, D.E. & Savaria, Y. (2000). A direct digitally delay generator. Communication présentée à 23rd International Semiconductor Conference (CAS 2000), Sinaia, Romania (p. 87-90).
      • Communication de conférence
        Vado, P., Savaria, Y., Zoccarato, Y. & Robach, C. (2000). A methodology for validating digital circuits with mutation testing. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2000), Geneva, Switzerland (p. 343-346).
      • Communication de conférence
        Hébert, O., Kraljic, I.C. & Savaria, Y. (2000). A method to derive application-specific embedded processing cores. Communication présentée à 8th International Workshop on Hardware/Software Codesign (CODES 2000), San Diego, CA, USA (p. 88-92).
      • Communication de conférence
        Cantin, M.-A., Blaquière, Y., Savaria, Y., Lavoie, P. & Granger, É. (2000). Analysis of quantization effects in a digital hardware implementation of a fuzzy ART neural network algorithm. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2000), Geneva, Switzerland (p. 141-144).
      • Communication de conférence
        Fouzar, Y., Sawan, M. & Savaria, Y. (2000). A new fully integrated CMOS phase-locked loop with low jitter and fast lock time. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2000), Geneva, Switzerland (p. 253-256).
      • Communication de conférence
        Fouzar, Y., Sawan, M. & Savaria, Y. (2000). CMOS Wide-Swing Differential VCO for Fully Integrated Fast PLL. Communication présentée à 43rd IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2000) (p. 948-950).
      • Communication de conférence
        Calbaza, D.E. & Savaria, Y. (2000). Direct digital frequency synthesis of low-jitter clocks. Communication présentée à IEEE Custom Integrated Circuits Conference, Orlando, FL, USA (p. 31-34).
      • Communication de conférence
        Boyer, F.R., Aboulhamid, E.M. & Savaria, Y. (2000). Efficient verification method for a class of multi-phase sequential circuits. Communication présentée à 7th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2000) (p. 510-515).
      • Communication de conférence
        Donfack, C., Sawan, M. & Savaria, Y. (2000). Fully integrated AC impedance measurement technique for implantable electrical stimulation applications. Communication présentée à 5th Annual Conference of the International Functional Electrical Stimulation Society (IFESS 2000), Denmark.
      • Communication de conférence
        Nsame, P., Grou-Szabo, R. & Savaria, Y. (2000). INTIME: a multi-tool specification environment for ensuring timing constraints integrity for SOC design. Communication présentée à IP Based Design 2000, Grenoble, France (p. 139-144).
      • Communication de conférence
        Calbaza, D.E. & Savaria, Y. (2000). Jitter model of direct digital synthesis clock generators. Communication présentée à TCAS-I 2000.
      • Communication de conférence
        Planque, F., Kraljic, I. & Savaria, Y. (2000). Mapping irregular algorithms in a custom computing image processing framework. Communication présentée à 3rd Annual Military and Aerospace Applications of Programmable Devices and Technologies International Conference (MAPLD 2000), Laurel, Maryland.
      • Communication de conférence
        Donfack, C., Sawan, M. & Savaria, Y. (2000). Techniques de caractérisation de l'interface électrode-tissus. Communication présentée à 2nd Symposium on Advanced Biomaterials (ISAB 2000), Montréal, Canada.
      • Communication de conférence
        Fouzar, Y., Sawan, M. & Savaria, Y. (2000). Very short locking time PLL based on controlled gain technique. Communication présentée à 7th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2000), Jounieh, Lebanon (p. 252-255).
    • 1999
      • Communication de conférence
        Antaki, B., Savaria, Y., Saman, A., Xiong, N., Borrione, D. & Ernst, R. (1999). Design for testability method for CML digital circuits. Communication présentée à Design, Automation and Test in Europe Conference and Exhibition (DATE 1999), Munich, Germany (p. 360-367).
      • Communication de conférence
        Cousineau, C., Laperle, F., Savaria, Y., Pocek, K.L. & Arnold, J.M. (1999). Design of a JTAG based run time reconfigurable system. Communication présentée à 7th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, Napa Valley, CA, USA (p. 268-269).
      • Communication de conférence
        Le Chapelain, B., Mechain, A., Savaria, Y. & Bois, G. (1999). Development of a high performance TSPC library for implementation of large digital building blocks. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 1999), Orlando, FL, USA (p. 443-446).
      • Communication de conférence
        Donfack, C., Sawan, M. & Savaria, Y. (1999). Efficient monitoring of electrodes-nerve contacts during FNS of the bladder. Communication présentée à 4th Annual Conference of the International Functional Electrical Stimulation Society (IFESS 1999), Sendai, Japon.
      • Communication de conférence
        Jiang, Y., Tang, Y., Wang, Y. & Savaria, Y. (1999). Evaluating the ouptput probability of boolean functions without floating point operations. Communication présentée à Canadian Conference on Electrical and Computer Engineering (CCECE 1999), Edmonton (p. 433-437).
      • Communication de conférence
        Calbaza, D.E. & Savaria, Y. (1999). Jitter model of direct digital synthesis clock generators. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 1999) (p. 1-4).
      • Communication de conférence
        Jin, Z.-F., Laurin, J.-J. & Savaria, Y. (1999). New approach to analyze interconnect delays in RC wire models. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 1999) (p. 246-249).
      • Communication de conférence
        Nsame, P. & Savaria, Y. (1999). Virtualising on-chip bus interfaces for improved embedded processor system performance. Communication présentée à IFIP International Workshop on IP Based Synthesis and System Design, Grenoble, France (p. 138-143).
    • 1998
      • Communication de conférence
        Fouzar, Y., Sawan, M. & Savaria, Y. (1998). A BiCMOS wide-lock range fully integrated PLL. Communication présentée à 10th International Conference on Microelectronics, Monastir, Tunisia (p. 274-277). Tiré de https://doi.org/10.1109/ICM.1998.825617
      • Communication de conférence
        Poire, P., Cantin, M.-A., Daniel, H., Blaquiere, Y., Savaria, Y., Pocek, K.L. & Arnold, J.M. (1998). A comparative analysis of fuzzy ART neural network implementations: the advantages of reconfigurable computing. Communication présentée à IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, CA, USA (p. 304-305). Tiré de https://doi.org/10.1109/FPGA.1998.707927
      • Communication de conférence
        Nekili, M., Savaria, Y., Bois, G., Bayoumi, M.A. & Jullien, G. (1998). Design of clock distribution networks in presence of process variations. Communication présentée à 8th Great Lakes Symposium on VLSI, Lafayette, LA, USA (p. 95-102).
      • Communication de conférence
        Savaria, Y., El Hassan, F., Khali, H. & Sawan, M. (1998). Effective hardware/software implementation of a viterbi decoder using an FPGA-based reconfigurable computing platform. Communication présentée à FDP 1998 (p. 161-165).
      • Communication de conférence
        Poire, P., Savaria, Y., Daniel, H., Cantin, M.a. & Blaquiere, Y. (1998). Hardware/software codesign of a Fuzzy ART neural clusterer : The benefits of configurable computing. Communication présentée à 3rd Conference on Configurable Computing, Boston MA, USA (p. 90-96).
      • Communication de conférence
        Cantin , M.-A., Blaquière, Y., Savaria, Y., Granger, E. & Lavoie, P. (1998). Implementation fo the Fuzzy ART neural network for fast clustering of radar pulses. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 1998), Monterey (p. 14-17).
      • Communication de conférence
        Boyer, F.R., Abiylhamid, E.M., Savaria, Y. & Bennour, I.E. (1998). Optical design of synchronous circuits using software pipeling techniques. Communication présentée à VLSI in Computers and Processors, Austin (p. 62-67).
      • Communication de conférence
        Marriott, P., Kraljic, I. & Savaria, Y. (1998). Parallel ultra large scale engine SIMD architectures for real time digital signal processing applications. Communication présentée à International Conference on Computer Design (ICCD 1998), Austin (p. 482-487).
      • Communication de conférence
        Audet, D., Masson, S. & Savaria, Y. (1998). Reducing fault sensitivity of microprocessor-based system by modifying workload structure. Communication présentée à IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Austin (p. 241-249).
      • Communication de conférence
        Audet, D., Masson, S. & Savaria, Y. (1998). Reducing fault sensitivity of microprocessor-based systems by modifying workload structure. Communication présentée à IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 1998), Austin, TX (p. 241-249). Tiré de https://doi.org/10.1109/DFTVS.1998.732172
      • Communication de conférence
        Chabini, N., Bennour, I.E., Aboulhamid, E.M. & Savaria, Y. (1998). Static method for system performance estimation. Communication présentée à 10th International Conference on Microelectronics.
    • 1997
      • Communication de conférence
        Bélanger, N., Antaki, B. & Savaria, Y. (1997). An algorithm for fast array transfers. Communication présentée à 11th Annual International Symposium on High Performance Computing Systems, Winnipeg, Man., Canada (p. 117-126).
      • Communication de conférence
        Gagnon, Y., Savaria, Y., Meunier, M. & Thibeault, C. (1997). Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model. Communication présentée à IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1997), Paris, Fr (p. 157-165).
      • Communication de conférence
        Khali, H., Savaria, Y. & Houle, J.L. (1997). Computational limits of homogeneous acceleration using lookup tables. Communication présentée à 11th Annual International Symposium on High Performance Computing Systems, Winnipeg, Man., Canada (p. 345-351).
      • Communication de conférence
        Kafrounni, M., Thibeault, C. & Savaria, Y. (1997). Cost model for VLSI/MCM systems. Communication présentée à IEEE Symposium on Defect and Fault Tolerance in VLSI Systems, Paris, France (p. 148-156).
      • Communication de conférence
        Bois, G., Bosi, B. & Savaria, Y. (1997). High performance reconfigurable coprocessor for digital signal processing. Communication présentée à 14th Annual International Conference of the Mentor Graphics Users' Group, Portland, Oregon.
      • Communication de conférence
        Lavoie, P., Crespo, J.F. & Savaria, Y. (1997). Multiple categorization using fuzzy ART. Communication présentée à IEEE International Conference on Neural Networks (ICNN 1997), Houston, TX, USA (p. 1983-1988).
      • Communication de conférence
        Hrytzak, R., Savaria, Y. & Goslin, G. (1997). Reconfigurable computing greatly simplifies system development. Communication présentée à DSP World Spring Design Conference (p. 271-286).
      • Communication de conférence
        Antaki, B., Patenaude, S., Trognon, L. & Savaria, Y. (1997). Study on split-output TSPC CMOS circuits. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 1997), Hong Kong, Hong Kong (p. 1892-1895).
      • Communication de conférence
        Pera, F., Savaria, Y. & Bois, G. (1997). Time delay measurement methods for integrated transmission lines and high speed cells characterization. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 1997), Hong Kong, Hong Kong (p. 293-296).
    • 1996
      • Communication de conférence
        Savaria, Y., Bois, G., Popovic, P. & Wayne, A. (1996). Computational acceleration methodologies: advantages of reconfigurable acceleration subsystems. Communication présentée à High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic (p. 195-205).
      • Communication de conférence
        Soufi, M., Rochon, S., Savaria, Y. & Kaminska, B. (1996). Design and performance of CMOS TSPC cells for high speed pseudo random testing. Communication présentée à 14th IEEE VLSI Test Symposium, Princeton, NJ, USA (p. 368-373).
      • Communication de conférence
        Audet, D., Gagnon, N. & Savaria, Y. (1996). Implementing fault injection and tolerance mechanisms in multiprocessor systems. Communication présentée à IEEE Workshop on Defect and Fault Tolerance in VLSI (DFT 1996), Boston (p. 310-317).
      • Communication de conférence
        Lejmi, S., Bois, G. & Savaria, Y. (1996). On the effects of retiming applied to self-checking sequential circuit. Communication présentée à 2nd IEEE On-Line Testing Workshop, Biaritz (p. 96-99).
      • Communication de conférence
        Lavoie, P., Crespo, J.-F. & Savaria, Y. (1996). On the stability of Fuzzy ART. Communication présentée à 18th Biennal Symposium on Communications, Kingston (p. 185-188).
      • Communication de conférence
        Audet, D., Gagnon, F. & Savaria, Y. (1996). Quantitative comparisons of TMR implementations in a multiprocessor system. Communication présentée à 3rd IEEE On-Line Testing Workshop, Biaritz (p. 196-199).
      • Communication de conférence
        Belhaouane, A., Savaria, Y. & Kaminska, B. (1996). Reconstruction method for data acquisition systems qith randomly distributed jitter. Communication présentée à 2nd IEEE International Mixed Signal Testing Workshop (p. 119-122).
      • Communication de conférence
        Granger, É., Blaquière, Y., Savaria, Y., Cantin, M.-A. & Lavoie, P. (1996). VLSI architecture for fast clustering with fuzzy ART neural networks. Communication présentée à 1st International Workshop on Neural Networks for Identification, Control, Robotics, and Signal/Image Processing (NICROSP 1996), Venice, Italy (p. 117-125).
    • 1995
      • Communication de conférence
        Sawan, M., St-Amand, R. & Savaria, Y. (1995). Design and optimization of programmable biphasic current-sources. Communication présentée à 2nd annual International Conference on Electronics, Circuits and Systems (ICECS 1995), Amman, Jordan (p. 169-173).
      • Communication de conférence
        Audet, D. & Savaria, Y. (1995). High-speed interconnections using true single-phase clocking. Communication présentée à 7th IEEE Annual International Conference on Wafer Scale Integration, San Francisco, Ca, USA (p. 258-267).
      • Communication de conférence
        Rzeszut, J., Kaminska, B. & Savaria, Y. (1995). New method for testing mixed analog and digital circuits. Communication présentée à 4th Asian Test Symposium, Bangalore, India (p. 127-132).
      • Communication de conférence
        Soufi, M., Savaria, Y. & Kaminska, B. (1995). On the design of at-speed testable VLSI circuits. Communication présentée à 13th IEEE VLSI Test Symposium, Princeton, NJ, USA (p. 290-295).
      • Communication de conférence
        Soufi, M., Savaria, Y. & Kaminska, B. (1995). On Using partial reset for pseudo-random testing. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 1995), Seattle, WA, USA (p. 949-952).
      • Communication de conférence
        Gadiri, A., Savaria, Y. & Kaminska, B. (1995). Optimized CMOS compatible photoreceiver. Communication présentée à Canadian Conference on Electrical and Computer Engineering (CCECE 1995), Montreal, Can (p. 211-214).
      • Communication de conférence
        Khali, H., Savaria, Y., Houle, J.L., Beraldin, J.A., Blais, F. & Rioux, M. (1995). VLSI chip for 3-D camera calibration. Communication présentée à Canadian Conference on Electrical and Computer Engineering (CCECE 1995), Montreal, Can (p. 120-123).
    • 1994
      • Communication de conférence
        Barwicz, A., Massicotte, D., Savaria, Y., Santerre, M.A. & Morawsi, R.Z. (1994). Application-specific processor dedicated to Kalman-filter-based correction od spectrometric data. Communication présentée à IEEE Instrumentation and Measurement Technology Conference (IMTC 1994), Hamamatsu, Japon (p. 352-356).
      • Communication de conférence
        Audet, D., Savaria, Y. & Arel, N. (1994). Architectural approach for increasing clock frequency and communication speed in monolithic-WSI systems. Communication présentée à 6th Annual IEEE International Conference on Wafer Scale Integration, San Francisco , California (p. 235-243).
      • Communication de conférence
        Nekili, M., Savaria, Y. & Bois, G. (1994). A variable-size parallel regenerator for long integrated interconnections. Communication présentée à 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA (p. 50-53).
      • Communication de conférence
        Ghannoum, S., Chtchvyrkov, D. & Savaria, Y. (1994). Comparative study of single-phase clocked latches using estimation criteria. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, England (p. 347-350).
      • Communication de conférence
        Kermouche, R. & Savaria, Y. (1994). Defect and fault tolerant scan chains. Communication présentée à IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1994), Montreal, Can (p. 185-193).
      • Communication de conférence
        St-Amand, R., Savaria, Y. & Sawan, M. (1994). Design optimization of a current source for microstimulator applications. Communication présentée à 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA (p. 129-132).
      • Communication de conférence
        Abderrahman, A., Kaminska, B. & Savaria, Y. (1994). Estimation of simultaneous switching power and ground noise of static CMOS combinational circuits. Communication présentée à European Design and Test Conference, Paris, Fr (p. 658).
      • Communication de conférence
        Savaria, Y., Chtchvyrkov, D. & Currie, J.F. (1994). Fast CMOS voltage-controlled ring oscillator. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, England (p. 359-362).
      • Communication de conférence
        Crespo, J.-F., Lavoie, P. & Savaria, Y. (1994). Fast convergence with low precision weights in ART1 networks. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, England (p. 237-240).
      • Communication de conférence
        Nekili, M., Savaria, Y. & Bois, G. (1994). Fast low-power driver for long interconnections in VLSI systems. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 1994), Londres (p. 343-346).
      • Communication de conférence
        St.-Amand, R., Sawan, M. & Savaria, Y. (1994). Generation of balanced bipolar stimuli based on current sources without coupling capacitor. Communication présentée à 16th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC 1994), Baltimore, MD, USA (p. 992-993).
      • Communication de conférence
        Kermouche, R., Savaria, Y. & Audet, D. (1994). Harvest model of an integrated hierarchical-bus architecture. Communication présentée à 6th Annual IEEE International Conference on Wafer Scale Integration, San Francisco, CA, USA (p. 69-78).
      • Communication de conférence
        BenHamida, N., Kaminska, B. & Savaria, Y. (1994). Pseudo-random vector compaction for sequential testability. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 1994), London, England (p. 63-66).
      • Communication de conférence
        Ghannoum, S., Chtchvyrkov, D. & Savaria, Y. (1994). Single-clock dynamic latches optimization. Communication présentée à 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA (p. 46-49).
      • Communication de conférence
        Kroumba, S.M., Bois, G. & Savaria, Y. (1994). Synthesis approach for the generation of parallel architectures. Communication présentée à 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA (p. 323-326).
    • 1993
      • Communication de conférence
        Crepeau, J., Thibeault, C. & Savaria, Y. (1993). Some results on yield and local design rule relaxation. Communication présentée à IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1993), Venice, Italy (p. 144-151). Tiré de https://doi.org/10.1109/DFTVS.1993.595745
  • Livres (1)
    • 2009
      • Livre
        Naderi, A., Sawan, M. & Savaria, Y. (2009). Undersampling delta-sigma modulators : theory, design and implementation. Lambert Academic Publishers.
  • Chapitres de livre (4)
    • 2016
      • Chapitre de livre
        Prieur, D., Granger, E., Savaria, Y. & Thibeault, C. (2016). Efficient identification of faces in video streams using low-power multi-core devices. Dans Handbook of pattern recognition and computer vision (5e éd.). World Scientific. Tiré de https://doi.org/10.1142/9789814656535_0023
    • 2015
      • Chapitre de livre
        Zarrabi, H., Al-Khalili, A.J. & Savaria, Y. (2015). Design intelligence for interconnection realization in power-managed SoCs. Dans Computational Intelligence in Digital and Network Designs and Applications (p. 69-96). Springer International Publishing. Tiré de https://doi.org/10.1007/978-3-319-20071-2_3
    • 2009
      • Chapitre de livre
        Mahoney, P., Savaria, Y., Bois, G. & Plante, P. (2009). Performance characterization for the implementation of content addressable memories based on parallel hashing memories. Dans Transactions on High-Performance Embedded Architectures and Compilers. II (p. 307-325). Berlin, Germany: Springer Verlag.
    • 2003
      • Chapitre de livre
        Loiseau, L. & Savaria, Y. (2003). Design reuse. Dans System-on-chip for real-time applications (p. 29-82). Luwer academic publishers.
  • Brevets (7)
    • 2013
      • Brevet
        Blaquièere, Y., Savaria, Y., Basile-Bellavance, Y., Valorge, O., Lahkssassi, A., André, W., Laflamme Mayer, N., Bougataya, M. & Sawan, M. (2013). Methods, apparatus and system to support large-scale micro- systems including embedded and distributed power supply, thermal regulation, multi-distributedsensors and electrical signal propagation (Brevet n° US 20130285739 - demande). Tiré de https://patents.google.com/patent/US20130285739
    • 2010
      • Brevet
        Gagnon, F., Savaria, Y., Dumais, P., Ammari, M.L. & Thibeault, C. (2010). Multiequalizer unit used for telecommunications has decision unit, which receives corresponding synchronized signals and choose one synchronized signal that matches with predetermined transmission performance criterion signal (Brevet n° US 7693490). Tiré de https://patents.google.com/patent/US7693490
    • 2009
      • Brevet
        Lacourse, A., Ducharme, M., St-Jean, H., Gagnon, Y., Savaria, Y. & Meunier, M. (2009). Tunable semiconductor component provided with a current barrier (Brevet n° US 7564078). Tiré de https://www.google.ca/patents/US7564078
    • 2006
      • Brevet
        Sawan, M., Harvey, J.-F., Roy, M., Coulombe, J., Savaria, Y. & Donfack, C. (2006). Body electronic implant and artificial vision system thereof (Brevet n° US 7027874). Tiré de https://patents.google.com/patent/US7027874
    • 2001
      • Brevet
        Gagnon, Y., Meunier, M. & Savaria, Y. (2001). Method and apparatus for iteratively, selectively tuning the impedance of integrated semiconductor devices using a focussed heating source (Brevet n° US 6329272). Tiré de https://www.google.ca/patents/US6329272
    • 2000
    • 1994
  • Rapports (8)
    • 2008
      • Rapport
        Hasan, S.R., Bélanger, N. & Savaria, Y. (2008). All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communication in DSM SoCs (Rapport n° EPM-RT-2008-10). École Polytechnique de Montréal. Tiré de https://publications.polymtl.ca/2632/
    • 2006
      • Rapport
        Trabelsi, A., Boyer, F.-R. & Savaria, Y. (2006). On the application of minimum noise tracking to cancel cosine shaped residual noise (Rapport n° EPM-RT-2006-09). École Polytechnique de Montréal. Tiré de https://publications.polymtl.ca/3157/
    • 2001
      • Rapport
        Granger, É., Savaria, Y. & Lavoie, P. (2001). A pattern reordering approach based on ambiguity detection for on-line category learning (Rapport n° EPM-RT-01-02). École Polytechnique de Montréal.
    • 1998
      • Rapport
        Savaria, Y. (1998). Study of neural networks for clustering radar signals: Final report (Rapport n° 98-610). Canada.
    • 1995
      • Rapport
        Audet, D., Savaria, Y. & Arel, N. (1995). Effective ultra large scale integration (ULSI) architecture techniques: FATMOS, a fault-tolerant multiprocessor operating system.
      • Rapport
        Audet, D. & Savaria, Y. (1995). Effective ultra large scale integration (ULSI) architecture techniques : the host interface.
      • Rapport
        Audet, D. & Savaria, Y. (1995). Effective ultra large scale integration (ULSI) architecture techniques : the routers, from a functional to a detailed implementation description.
    • 1994
      • Rapport
        Nekili, M., Bois, G. & Savaria, Y. (1994). Deterministic skew modeling and high-speed clocking of large integrated systems by using logic-based & hybrid H-trees (Rapport n° EPM-RT-94-09). École Polytechnique de Montréal.