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Tarek Ould-Bachir
B. Eng. M.A.Sc., Ph.D. (Poly)
  Publications
Assistant Professor
Department of Computer Engineering and Software Engineering
Phone: (514) 340-4711 Ext. 2452 Fax: (514) 340-5139 Room: M-5107
Areas of expertise
Digital signal processing Computer hardware Computer systems organization Distributed and parallel processing Computer architecture and design VLSI systems Mathematical modelling Control systems Modelling, simulation Modelling and simulation studies
Google Scholar ResearchGate

Research interests and affiliations

Research interests
  • Digital systems
  • High-level synthesis
  • Real-time systems
  • Embedded systems
  • Computer arithmetic
  • High performance computing
  • Cyber-physical systems
  • Cyber-physical systems security
  • Computer architecture
  • Specialized architectures
  • Field-programmable gate arrays (FPGAs)
Expertise type(s) (NSERC subjects)
  • 2514 Digital signal processing
  • 2701 Computer hardware
  • 2702 Computer systems organization
  • 2704 Distributed and parallel processing
  • 2719 Computer architecture and design
  • 2722 VLSI systems

Publications

Recent publications
Journal article
Ould-Bachir, T., Chalangar, H., Sheshyekani, K. & Mahseredjian, J. (2021). High performance computing engines for the FPGA-based simulation of the ULM. Electric Power Systems Research, 190, 7 pages. Retrieved from https://doi.org/10.1016/j.epsr.2020.106716
Journal article
Montaño, F., Ould-Bachir, T. & David, J.P. (2020). A Latency-Insensitive Design Approach to Programmable FPGA-Based Real-Time Simulators. Electronics, 9(11), 21 pages. Retrieved from https://doi.org/10.3390/electronics9111838
Journal article
Chalangar, H., Ould-Bachir, T., Sheshyekani, K., Li, S. & Mahseredjian, J. (2020). Evaluation of a Constant Parameter Line-based TWFL Real-Time Testbed. IEEE Transactions on Power Delivery, 35(2), 1010-1019. Retrieved from https://doi.org/10.1109/TPWRD.2019.2933984
Conference paper
Montano, F., Ould-Bachir, T., Mahseredjian, J. & David, J.P. (2019). A Low-Latency Reconfigurable Multistage Interconnection Network. Paper presented at the IEEE Canadian Conference of Electrical and Computer Engineering (CCECE 2019), Edmonton, AB, Canada (4 pages). Retrieved from https://doi.org/10.1109/CCECE.2019.8861540
See all publications (29)

Biography

Tarek Ould-Bachir received the M.A.Sc. and Ph.D. degrees in electrical engineering from the Polytechnique Montréal, in 2008 and 2013, respectively. From 2007 to 2018, he was with OPAL-RT Technologies, holding various positions in the R&D Department. From 2018 to 2020, he was a Research Associate with Polytechnique Montréal. He is currently an Assistant Professor with the Computer and Software Engineering Department at Polytechnique Montréal.

Teaching

  • ELE1300, Digital Design
  • INF1600, Computer Organization 
  • INF2010, Algorithms and data structures
  • INF3500, Digital Design II
  • INF3610, Embedded Systems

Supervision at Polytechnique

IN PROGRESS

  • Ph.D. (4)

    • Allabadi, Ahmad. Numerical methods for power electronics based power systems.
    • Chalangar, Hossein. FPGA-based Real-Time Simulation of High Switching Frequency Converters.
    • Masoom, Alireza. High-level programming methods for the simulation of power system transients.
    • Montano, Federico. A method for the FPGA-based Real-Time Simulation of Power Converters.

  • Master (thesis) (6)

    • Dourid, Issam.
    • Najam, Mouad.
    • Mashreghi Moghadam, Parisa. P4-programmable packet parser FPGA overlay .
    • Ould Mohamed, Nassim. Contrôle prédictif de convertisseurs de puissance sur FPGA.
    • Makhroute, El Mahdi .
    • El Harti, Mohamed Ayoub.

  • Undergraduate (3)

    • Gallay, Andy.
    • Boucher-Charest, Benjamin.
    • Zeghaida, Aymen-Alaeddine.