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Guy Bois (79)

  • Articles de revue (18)
    • 2016
      • Article de revue
        Vakili, S., Langlois, J.M.& Bois, G. (2016). Accuracy-aware processor customisation for fixed-point arithmetic. IET Computers and Digital Techniques, 10(1), 11 pages. Tiré de https://doi.org/10.1049/iet-cdt.2014.0188
    • 2013
      • Article de revue
        Vakili, S., Langlois, J.M.P. & Bois, G. (2013). Customised soft processor design: A compromise between architecture description languages and parameterisable processors. IET Computers and Digital Techniques, 7(3), 122-131. Tiré de https://doi.org/10.1049/iet-cdt.2012.0088
      • Article de revue
        Vakili, S., Langlois, J.M.P. & Bois, G. (2013). Enhanced precision analysis for accuracy-aware bit-width optimization using affine arithmetic. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(12), 1853-1865. Tiré de https://doi.org/10.1109/TCAD.2013.2277978
      • Article de revue
        Le Beux, S., O'Connor, I., Nicolescu, G., Bois, G. & Paulin, P. (2013). Reduction methods for adapting optical network on chip topologies to 3D architectures. Microprocessors and Microsystems, 37(1), 87-98.
    • 2010
      • Article de revue
        Le Beux, S., Bois, G., Nicolescu, G., Bouchebaba, Y., Langevin, M. & Paulin, P. (2010). Combining mapping and partitioning exploration for NoC-based embedded systems. Journal of Systems Architecture, 56(7), 223-232.
      • Article de revue
        Le Beux, S., Trajkovic, J., O'Connor, I., Nicolescu, G., Bois, G. & Paulin, P. (2010). Multi-optical network-on-chip for large scale MPSoC. IEEE Embedded Systems Letters, 2(3), 77-80.
    • 2009
      • Article de revue
        Beucher, N., Belanger, N., Savaria, Y. & Bois, G. (2009). High acceleration for video processing applications using specialized instruction set based on parallelism and data reuse. Journal of Signal Processing Systems, 56(2-3), 155-165.
      • Article de revue
        Zaki, M.H., Denman, W., Tahar, S. & Bois, G. (2009). Integrating abstraction techniques for formal verification of analog designs. Journal of Aerospace Computing, Information and Communication, 6(5), 373-392.
    • 2008
      • Article de revue
        Zaki, M.H., Tahar, S. & Bois, G. (2008). Formal verification of analog and mixed signal designs: A survey. Microelectronics Journal, 39(12), 1395-1404.
    • 2006
      • Article de revue
        Chevalier, J.M., De Nanclas, M., Filion, L., Benny, O., Rondonneau, M., Bois, G. & Aboulhamid, E.M. (2006). A Systemc Refinement Methodology for Embedded Software. IEEE Design & Test of Computers, 23(2), 148-158.
    • 2004
      • Article de revue
        Dubois, M., Bois, G. & Savaria, Y. (2004). Double profiling methodology for video processing platform. WSEAS Transactions on Computers, 3(6), 1802-1807.
      • Article de revue
        Lapalme, J., Aboulhamed, E.M., Nicolescu, G., Charest, L., Boyer, F.R., David, J.P. & Bois, G. (2004). Esys.net: A New Solution for Embedded Systems Modeling and Simulation. ACM Sigplan Notices, 39(7), 107-114. Tiré de https://doi.org/10.1145/997163.997179
      • Article de revue
        Cyr, G., Bois, G. & Aboulhamid, M. (2004). Generation of processor interface for SoC using standard communication protocol. IEE Proceedings. Computers and Digital Techniques, 151(5), 367-376.
    • 2003
      • Article de revue
        Beaudin, S., Marceau, R.J., Bois, G., Savaria, Y. & Kandil, N. (2003). An Economic Parallel Processing Technology for Faster Than Real-Time Transient Stability Simulation. European Transactions on Electrical Power, 13(2), 105-112.
    • 1999
      • Article de revue
        Bosi, B., Bois, G. & Savaria, Y. (1999). Reconfigurable Pipelined 2-D Convolvers for Fast Digital Signal Processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7(3), 299-308.
      • Article de revue
        Nekili, M., Savaria, Y. & Bois, G. (1999). Spatial Characterization of Process Variations Via Mos Transistor Time Constants in Vlsi and Wsi. IEEE Journal of Solid-State Circuits, 34(1), 80-84.
    • 1997
      • Article de revue
        Nekili, M., Bois, G. & Savaria, Y. (1997). Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 5(2), 161-174.
    • 1996
      • Article de revue
        Bois, G. & Cerny, E. (1996). Efficient generation of diagonal constraints for 2-D mask compaction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(9), 1119-1126.
  • Communications de conférence (57)
    • 2016
      • Communication de conférence
        Montero, F., Bois, G., Jenn, E. & Duplantier, K. (2016). Architectural exploration and implementation of an image processing chain with SpaceStudio. Communication présentée à 26th International Conference on Field Programmable Logic and Applications (FPL 2016), Lausanne, Switzerland (p. 1 page). Tiré de https://doi.org/10.1109/FPL.2016.7577388
      • Communication de conférence
        Lacroix, A.B., Langlois, J.M.P., Boyer, F.-R., Gosselin, A. & Bois, G. (2016). Node configuration for the Aho-Corasick algorithm in intrusion detection systems. Communication présentée à 12th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2016), Santa Clara, California (p. 121-122). Tiré de https://doi.org/10.1145/2881025.2889473
    • 2015
      • Communication de conférence
        Nsame, P., Bois, G. & Savaria, Y. (2015). Analysis and characterization of data energy tradeoffs: for VLSI architectural agility in C-RAN platforms. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2015), Lisbon, Portugal (p. 1466-1469). Tiré de https://doi.org/10.1109/ISCAS.2015.7168921
      • Communication de conférence
        Vakili, S., Langlois, J.M.P. & Bois, G. (2015). Designing Customized Microprocessors for Fixed-Point Computation. Communication présentée à NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2015), Montréal Canada. Tiré de https://doi.org/10.1109/AHS.2015.7231168
      • Communication de conférence
        Landry, K., Boland, J.-F. & Bois, G. (2015). Integration and Performances Analysis of a Data Distribution Service Middleware in Avionics. Communication présentée à SAE AeroTech Congress and Exhibition (AEROTECH 2015), Seattle, WA, United states. Tiré de https://doi.org/10.4271/2015-01-2554
      • Communication de conférence
        Gaudon, M., Bois, G., Hugues, J. & Monteiro, F. (2015). Performance verification for ESL design methodology from AADL models. Communication présentée à International Symposium on Rapid System Prototyping (RSP 2015), Amsterdam, NL (p. 33-37). Tiré de https://doi.org/10.1109/RSP.2015.7416543
    • 2014
      • Communication de conférence
        Nsame, P., Bois, G. & Savaria, Y. (2014). Adaptive real-time DSP acceleration for SoC applications. Communication présentée à 57th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2014), College Station, TX (p. 298-301). Tiré de https://doi.org/10.1109/MWSCAS.2014.6908411
      • Communication de conférence
        Nsame, P., Bois, G. & Savaria, Y. (2014). A data-driven energy efficient and flexible compute fabric architecture: For adaptive computing applied to ULSI of FFT. Communication présentée à 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS 2014), Marseille, France (p. 750-753). Tiré de https://doi.org/10.1109/ICECS.2014.7050094
      • Communication de conférence
        Benyoussef, M., Boland, J.-F., Nicolescu, G., Bois, G. & Hugues, J. (2014). Design space exploration: bridging the gap between high-level models and virtual execution platforms. Communication présentée à Embedded Real Time System and Software Congress (ERTS2 2014), Toulouse, France (10 pages).
    • 2013
      • Communication de conférence
        Bois, G. (2013). End-to-end automated HW/SW co-design for reconfigurable SoC. Communication présentée à Electronic Design Process Symposium (EDPS 2013), Monterey, Calif.
      • Communication de conférence
        Vakili, S., Langlois, J.M.P. & Bois, G. (2013). Finite-precision error modeling using affine arithmetic. Communication présentée à 38th IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2013), Vancouver, BC, Canada (p. 2591-2595).
      • Communication de conférence
        Savard, J., Bao, L., Bois, G. & Boland, J.-F. (2013). Model-based design flow driven by integrated modular avionic simulations. Communication présentée à SAE AeroTech Congress and Exhibition (AEROTECH 2013), Montreal, QC, Canada.
    • 2012
      • Communication de conférence
        Moss, L., Guerard, H., Dare, G. & Bois, G. (2012). An ESL methodology for rapid creation of embedded aerospace systems using hardware-software co-design on virtual platforms. Communication présentée à SAE 2012 Aerospace Electronics and Avionics Systems Conference, Phoenix, AZ (10 pages). Tiré de https://doi.org/10.4271/2012-01-2133
      • Communication de conférence
        Boland, J.-F., Bois, G. & Oudet, J.-P. (2012). Novel methodologies to support the architectural exploration of safety-critical systems. Communication présentée à Recherche et Innovation pour les Transports du Futur (RITF 2012), Paris, France.
      • Communication de conférence
        Pollina, M., Leclerc, Y., Conquet, E., Bois, G. & Moss, L. (2012). The Assert Set of Tools for Engineering (TASTE): demonstrator, HW/SW codesign and future evolution. Communication présentée à Embedded Real Time Software and Systems (ERTS2 2012), Toulouse, France (4 pages).
    • 2011
      • Communication de conférence
        Carmel-Veilleux, T., Boland, J.-F. & Bois, G. (2011). A novel low-overhead flexible instrumentation framework for virtual platforms. Communication présentée à 22nd IEEE International Symposium on Rapid System Prototyping (RSP 2011), Karlsruhe, Germany (p. 92-98).
      • Communication de conférence
        Vakili, S., Gil, D.C., Langlois, J.M.P., Savaria, Y. & Bois, G. (2011). Customized embedded processor design for global photographic tone mapping. Communication présentée à 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon (p. 382-385).
      • Communication de conférence
        Le Beux, S., Trajkovic, J., O'Connor, I., Nicolescu, G., Bois, G. & Paulin, P. (2011). Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology. Communication présentée à 14th Design, Automation and Test in Europe Conference and Exhibition (DATE 2011), Grenoble, France (p. 788-793).
    • 2010
      • Communication de conférence
        Le Beux, S., Nicolescu, G., Bois, G. & Paulin, P. (2010). A system-level exploration flow for optical network on chip (ONoC) in 3D MPSoC. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France (p. 3613-3616).
      • Communication de conférence
        Rogers-Vallee, M., Cantin, M.-A., Moss, L. & Bois, G. (2010). IP characterization methodology for fast and accurate power consumption estimation at transactional level model. Communication présentée à IEEE International Conference on Computer Design (ICCD 2010), Amsterdam, Netherlands (p. 534-541).
    • 2009
      • Communication de conférence
        Le Beux, S., Nicolescu, G., Bois, G., Bouchebaba, Y., Langevin, M. & Paulin, P. (2009). Optimizing configuration and application mapping for MPSoC architectures. Communication présentée à NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2009), San Francisco, California (p. 474-481).
    • 2008
      • Communication de conférence
        Fontaine, S., Goyette, S., Langlois, J.M.P. & Bois, G. (2008). Acceleration of a target tracking algo-rithm using an application specific instruction set processor. Communication présentée à IEEE International Conference on Computer Design (ICCD 2008).
      • Communication de conférence
        Moss, L., Cantin, M.-A., Bois, G. & Aboulhamid, E.M. (2008). Automation of communication refinement and hardware synthesis within a system-level design methodology. Communication présentée à 19th IEEE/IFIP International Symposium on Rapid System Prototyping (p. 75-81).
      • Communication de conférence
        Fontaine, S., Filion, L. & Bois, G. (2008). Exploring ISS abstractions for embedded software design. Communication présentée à 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 2008) (p. 651-655).
    • 2007
      • Communication de conférence
        Moss, L., De Nanclas, M., Filion, L., Fontaine, S., Bois, G. & Aboulhamid, M. (2007). Seamless hardware/software performance co-monitoring in a codesign simulation environment with RTOS support. Communication présentée à Design, Automation and Test in Europe Conference and Exhibition (DATE 2007), Nice Acropolis, France (p. 876-881).
    • 2006
      • Communication de conférence
        Provost, S., Lavigueur, B., Bois, G. & Nicolescu, G. (2006). Integration of Configurable Processors in a Multiprocessor Platform. Communication présentée à IEEE International SOC Conference (SOCC 2006) (p. 221-224).
      • Communication de conférence
        Deslauriers, F., Langevin, M., Bois, G., Savaria, Y. & Paulin, P. (2006). RoC: a scalable network on chip based on the token ring concept. Communication présentée à 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada.
    • 2005
      • Communication de conférence
        Dubois, M., Savaria, Y. & Bois, G. (2005). A Generic Ahb Bus for Implementing High-Speed Locally Synchronous Islands. Communication présentée à IEEE SoutheastCon 2004, Fort Lauderdale, Florida, USA (p. 11-16).
      • Communication de conférence
        Thibeault, J.F., Hubin, M., Deslauriers, F., Samson, P. & Bois, G. (2005). A Reprogrammable Soc Design for a Real-Time Control Application. Communication présentée à IEEE International Conference on Microelectronic Systems Education (MSE 2005), Anaheim, California, USA (p. 73-74).
      • Communication de conférence
        Mahoney, P., Savaria, Y., Bois, G. & Plante, P. (2005). Parallel hashing memories : an alternative to content addressable memories. Communication présentée à 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Quebec City, Que., Canada (p. 223-226).
    • 2004
      • Communication de conférence
        Quinn, D., Lavigueur, B., Bois, G. & Aboulhamid, M. (2004). A system level exploration platform and methodology for network applications based on configurable processors. Communication présentée à Design, Automation and Test in Europe Conference and Exhibition (DATE 2004), Paris, France (p. 364-369).
      • Communication de conférence
        Lapalme, J., Aboulhamid, E.M., Nicolescu, G., Charest, L., Boyer, F.R., David, J.P. & Bois, G. (2004). .Net framework - A solution for the next generation tools for system-level modeling and simulation. Communication présentée à Design, Automation and Test in Europe Conference and Exhibition (DATE 2004), Paris, France (p. 732-733). Tiré de https://doi.org/10.1109/DATE.2004.1268952
      • Communication de conférence
        Benny, O., Rondonneau, M., Chevalier, J., Bois, G., Aboulhamid, E.M. & Boyer, F.-R. (2004). SoC software refinement approach for a systemC platform. Communication présentée à Design & Verification Conference & Exhibition (DVCon 2004), San Jose, California.
      • Communication de conférence
        Chevalier, J., Benny, O., Rondonneau, M., Bois, G., Aboulhamid, E.M. & Boyer, F.R. (2004). Space: a Hardware/Software Systemc Modeling Platform Including an Rtos. Communication présentée à Forum on Specification and Design Languages (FDL 2003) (p. 91-104).
      • Communication de conférence
        Regimbal, S., Savaria, Y. & Bois, G. (2004). Verification strategy determination using dependence analysis of transaction-level models. Communication présentée à 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada (p. 87-92).
    • 2003
      • Communication de conférence
        Bertola, M. & Bois, G. (2003). A methodology for the design of AHB bus master wrappers. Communication présentée à Euromicro Symposium on Digital System Design (p. 90-95).
      • Communication de conférence
        Regimbal, S., Lemire, J.F., Savaria, Y., Bois, G., Aboulhamid, M. & Baron, A. (2003). Aspect Partitioning for Hardware Verification Reuse. Communication présentée à System-on-Chip for Real-Time Applications (p. 51-60).
      • Communication de conférence
        Regimbal, S., Lemire, J.-F., Savaria, Y., Bois, G., Aboulhamid, E.M. & Baron, A. (2003). Automating functional coverage analysis based on an executable specification. Communication présentée à 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (p. 228-234).
      • Communication de conférence
        Bissou, J.P., Dubois, M., Savaria, Y. & Bois, G. (2003). High-speed system bus for a SoC network processing platform. Communication présentée à 15th International Conference on Microelectronics (ICM 2003), Cairo, Egypt (p. 194-197). Tiré de https://doi.org/10.1109/ICM.2003.238564
      • Communication de conférence
        Pepga bissou, J., Dubois, M., Savaria, Y. & Bois, G. (2003). High speed system bus for a SoC network processing platform. Communication présentée à 15th International Conference on Microelectronics (ICM 2003), Le Caire, Égypte (p. 194-197).
      • Communication de conférence
        Lemire, J.F., Aboulhamid, E.M., Savaria, Y., Bois, G. & Baron, A. (2003). Implementing e assertion checkers from an SDL executable specifications. Communication présentée à DVCON, San José, USA.
      • Communication de conférence
        Bertola, M. & Bois, G. (2003). Teaching Bus Architectures With a Basic, Hands-on Soc Platform. Communication présentée à IEEE International Conference on Microelectronic Systems Education (MSE 2003) (p. 68-69).
      • Communication de conférence
        Filion, L., Chevalier, W., Bois, G. & Aboulhamid, E.A. (2003). The Syslib-Picasso Methodology for the Co-Design Specification Capture Phase. Communication présentée à System-on-Chip for Real-Time Applications (p. 183-192).
    • 2001
      • Communication de conférence
        Heneault, Y., Filion, L., Bois, G. & Aboulhamid, E.M. (2001). A Fast Hardware Co-Specification and Co-Simulation Methodology Integrated in a H/S Co-Design Platform. Communication présentée à 13th International Conference on Microelectronics (ICM 2001) (p. 253-256).
      • Communication de conférence
        Nekili, M., Savaria, Y. & Bois, G. (2001). Minimizing process-induced skew using elay tuning. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2001), Sydney, Australie (p. 426-429).
    • 1999
      • Communication de conférence
        Le Chapelain, B., Mechain, A., Savaria, Y. & Bois, G. (1999). Development of a high performance TSPC library for implementation of large digital building blocks. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 1999), Orlando, FL, USA (p. 443-446).
    • 1998
      • Communication de conférence
        Nekili, M., Savaria, Y., Bois, G., Bayoumi, M.A. & Jullien, G. (1998). Design of clock distribution networks in presence of process variations. Communication présentée à 8th Great Lakes Symposium on VLSI, Lafayette, LA, USA (p. 95-102).
      • Communication de conférence
        Shaditalab, M., Bois, G., Sawan, M., Pocek, K.L. & Arnold, J.M. (1998). Self-sorting radix-2 FFT on FPGAs using parallel pipelined distributed arithmetic blocks. Communication présentée à IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, CA, USA (p. 337-338). Tiré de https://doi.org/10.1109/FPGA.1998.707943
    • 1997
      • Communication de conférence
        Bois, G., Bosi, B. & Savaria, Y. (1997). High performance reconfigurable coprocessor for digital signal processing. Communication présentée à 14th Annual International Conference of the Mentor Graphics Users' Group, Portland, Oregon.
      • Communication de conférence
        Pera, F., Savaria, Y. & Bois, G. (1997). Time delay measurement methods for integrated transmission lines and high speed cells characterization. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 1997), Hong Kong, Hong Kong (p. 293-296).
    • 1996
      • Communication de conférence
        Savaria, Y., Bois, G., Popovic, P. & Wayne, A. (1996). Computational acceleration methodologies: advantages of reconfigurable acceleration subsystems. Communication présentée à High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic (p. 195-205).
      • Communication de conférence
        Lejmi, S., Bois, G. & Savaria, Y. (1996). On the effects of retiming applied to self-checking sequential circuit. Communication présentée à 2nd IEEE On-Line Testing Workshop, Biaritz (p. 96-99).
    • 1994
      • Communication de conférence
        Nekili, M., Savaria, Y. & Bois, G. (1994). A variable-size parallel regenerator for long integrated interconnections. Communication présentée à 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA (p. 50-53).
      • Communication de conférence
        Nekili, M., Savaria, Y. & Bois, G. (1994). Fast low-power driver for long interconnections in VLSI systems. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 1994), Londres (p. 343-346).
      • Communication de conférence
        Kroumba, S.M., Bois, G. & Savaria, Y. (1994). Synthesis approach for the generation of parallel architectures. Communication présentée à 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA (p. 323-326).
  • Chapitres de livre (2)
    • 2009
      • Chapitre de livre
        Mahoney, P., Savaria, Y., Bois, G. & Plante, P. (2009). Performance characterization for the implementation of content addressable memories based on parallel hashing memories. Dans Transactions on High-Performance Embedded Architectures and Compilers. II (p. 307-325). Berlin, Germany: Springer Verlag.
    • 2004
      • Chapitre de livre
        Bois, G., Filion, L., Tsikhanovich, A. & Aboulhamid, E.M. (2004). Modélisation, raffinement et programmation orientée objet avec SystemC. Dans Spécification et validation des systèmes monopuces (p. 171-208). Lavoisier.
  • Rapports (2)
    • 2009
      • Rapport
        Moss, L. & Bois, G. (2009). On the Scott-continuity of tagged signal processes (Rapport n° EPM-RT-2009-01). École Polytechnique de Montréal. Tiré de https://publications.polymtl.ca/2640/
    • 1994
      • Rapport
        Nekili, M., Bois, G. & Savaria, Y. (1994). Deterministic skew modeling and high-speed clocking of large integrated systems by using logic-based & hybrid H-trees (Rapport n° EPM-RT-94-09). École Polytechnique de Montréal.