Girard, S.R., Legault, V., Bois, G. & Boland, J.-F. (2019). Avionics Graphics Hardware Performance Prediction with Machine Learning. Scientific Programming, 2019, 15 pages. Tiré de https://doi.org/10.1155/2019/9195845
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Bois, Guy
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Bois, Guy
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Article de revue (18)
Communication de conférence (60)
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Chapitre de livre (8)
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Guy Bois (88)
- Articles de revue (18)
- 2019
Article de revue
- 2016
Article de revue Vakili, S., Langlois, J.M.P. & Bois, G. (2016). Accuracy-aware processor customisation for fixed-point arithmetic. IET Computers and Digital Techniques, 10(1), 11 pages. Tiré de https://doi.org/10.1049/iet-cdt.2014.0188
- 2013
Article de revue Vakili, S., Langlois, J.M.P. & Bois, G. (2013). Customised soft processor design: A compromise between architecture description languages and parameterisable processors. IET Computers and Digital Techniques, 7(3), 122-131. Tiré de https://doi.org/10.1049/iet-cdt.2012.0088Article de revue Vakili, S., Langlois, J.M.P. & Bois, G. (2013). Enhanced precision analysis for accuracy-aware bit-width optimization using affine arithmetic. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 32(12), 1853-1865. Tiré de https://doi.org/10.1109/TCAD.2013.2277978Article de revue Le Beux, S., O'Connor, I., Nicolescu, G., Bois, G. & Paulin, P. (2013). Reduction methods for adapting optical network on chip topologies to 3D architectures. Microprocessors and Microsystems, 37(1), 87-98. Tiré de https://doi.org/10.1016/j.micpro.2012.11.001
- 2010
Article de revue Le Beux, S., Bois, G., Nicolescu, G., Bouchebaba, Y., Langevin, M. & Paulin, P. (2010). Combining mapping and partitioning exploration for NoC-based embedded systems. Journal of Systems Architecture, 56(7), 223-232. Tiré de https://doi.org/10.1016/j.sysarc.2010.03.005Article de revue Le Beux, S., Trajkovic, J., O'Connor, I., Nicolescu, G., Bois, G. & Paulin, P. (2010). Multi-optical network-on-chip for large scale MPSoC. IEEE Embedded Systems Letters, 2(3), 77-80. Tiré de https://doi.org/10.1109/LES.2010.2057407
- 2009
Article de revue Beucher, N., Belanger, N., Savaria, Y. & Bois, G. (2009). High acceleration for video processing applications using specialized instruction set based on parallelism and data reuse. Journal of Signal Processing Systems, 56(2-3), 155-165. Tiré de https://doi.org/10.1007/s11265-008-0230-6Article de revue Zaki, M.H., Denman, W., Tahar, S. & Bois, G. (2009). Integrating abstraction techniques for formal verification of analog designs. Journal of Aerospace Computing, Information and Communication, 6(5), 373-392. Tiré de https://doi.org/10.2514/1.44289
- 2008
Article de revue Zaki, M.H., Tahar, S. & Bois, G. (2008). Formal verification of analog and mixed signal designs: A survey. Microelectronics Journal, 39(12), 1395-1404. Tiré de https://doi.org/10.1016/j.mejo.2008.05.013
- 2006
Article de revue Chevalier, J.M., De Nanclas, M., Filion, L., Benny, O., Rondonneau, M., Bois, G. & Aboulhamid, E.M. (2006). A Systemc Refinement Methodology for Embedded Software. IEEE Design & Test of Computers, 23(2), 148-158. Tiré de https://doi.org/10.1109/MDT.2006.27
- 2004
Article de revue Dubois, M., Bois, G. & Savaria, Y. (2004). Double profiling methodology for video processing platform. WSEAS Transactions on Computers, 3(6), 1802-1807.Article de revue Cyr, G., Bois, G. & Aboulhamid, M. (2004). Generation of processor interface for SoC using standard communication protocol. IEE Proceedings. Computers and Digital Techniques, 151(5), 367-376. Tiré de https://doi.org/10.1049/ip-cdt:20040915
- 2003
Article de revue Beaudin, S., Marceau, R.J., Bois, G., Savaria, Y. & Kandil, N. (2003). An Economic Parallel Processing Technology for Faster Than Real-Time Transient Stability Simulation. European Transactions on Electrical Power, 13(2), 105-112. Tiré de https://doi.org/10.1002/etep.4450130205
- 1999
Article de revue Bosi, B., Bois, G. & Savaria, Y. (1999). Reconfigurable Pipelined 2-D Convolvers for Fast Digital Signal Processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7(3), 299-308. Tiré de https://doi.org/10.1109/92.784091Article de revue Nekili, M., Savaria, Y. & Bois, G. (1999). Spatial Characterization of Process Variations Via Mos Transistor Time Constants in Vlsi and Wsi. IEEE Journal of Solid-State Circuits, 34(1), 80-84. Tiré de https://doi.org/10.1109/4.736658
- 1997
Article de revue Nekili, M., Bois, G. & Savaria, Y. (1997). Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 5(2), 161-174. Tiré de https://doi.org/10.1109/92.585214
- 1996
Article de revue Bois, G. & Cerny, E. (1996). Efficient generation of diagonal constraints for 2-D mask compaction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(9), 1119-1126. Tiré de https://doi.org/10.1109/43.536717
- 2019
- Communications de conférence (60)
- 2022
Communication de conférence Posso, J., Bois, G. & Savaria, Y. (2022). Mobile-URSONet: an Embeddable Neural Network for Onboard Spacecraft Pose Estimation. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2022), Austin, TX, USA (p. 794-798). Tiré de https://doi.org/10.1109/ISCAS48785.2022.9937721
- 2018
Communication de conférence Bois, G. (2018). Specific needs for the modelling and the refinement of CPU and FPGA platforms. Communication présentée à European Network on High Performance and Embedded Architecture and Compilation (HIPEAC 2018), Manchester, England.
- 2017
Communication de conférence Bois, G., Guerard, H. & Jenn, E. (2017). Using virtual platforms for early architectural exploration : experimentation on an image processing system. Communication présentée à 54th Design Automation Conference (DAC 2017), Austin, Texas. Tiré de https://www.dac.com/portals/0/documents/conference/54dac_program_web_1.pdf
- 2016
Communication de conférence Montero, F., Bois, G., Jenn, E. & Duplantier, K. (2016). Architectural exploration and implementation of an image processing chain with SpaceStudio. Communication présentée à 26th International Conference on Field Programmable Logic and Applications (FPL 2016), Lausanne, Switzerland (1 page). Tiré de https://doi.org/10.1109/FPL.2016.7577388Communication de conférence Lacroix, A.B., Langlois, J.M.P., Boyer, F.-R., Gosselin, A. & Bois, G. (2016). Node configuration for the Aho-Corasick algorithm in intrusion detection systems. Communication présentée à 12th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2016), Santa Clara, California (p. 121-122). Tiré de https://doi.org/10.1145/2881025.2889473
- 2015
Communication de conférence Nsame, P., Bois, G. & Savaria, Y. (2015). Analysis and characterization of data energy tradeoffs: for VLSI architectural agility in C-RAN platforms. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2015), Lisbon, Portugal (p. 1466-1469). Tiré de https://doi.org/10.1109/ISCAS.2015.7168921Communication de conférence Vakili, S., Langlois, J.M.P. & Bois, G. (2015). Designing Customized Microprocessors for Fixed-Point Computation. Communication présentée à NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2015), Montréal, Québec. Tiré de https://doi.org/10.1109/AHS.2015.7231168Communication de conférence Landry, K., Boland, J.-F. & Bois, G. (2015). Integration and Performances Analysis of a Data Distribution Service Middleware in Avionics. Communication présentée à SAE AeroTech Congress and Exhibition (AEROTECH 2015), Seattle, WA, United states. Tiré de https://doi.org/10.4271/2015-01-2554Communication de conférence Gaudon, M., Bois, G., Hugues, J. & Monteiro, F. (2015). Performance verification for ESL design methodology from AADL models. Communication présentée à International Symposium on Rapid System Prototyping (RSP 2015), Amsterdam, Netherlands (p. 33-37). Tiré de https://doi.org/10.1109/RSP.2015.7416543
- 2014
Communication de conférence Nsame, P., Bois, G. & Savaria, Y. (2014). Adaptive real-time DSP acceleration for SoC applications. Communication présentée à 57th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2014), College Station, TX (p. 298-301). Tiré de https://doi.org/10.1109/MWSCAS.2014.6908411Communication de conférence Nsame, P., Bois, G. & Savaria, Y. (2014). A data-driven energy efficient and flexible compute fabric architecture: For adaptive computing applied to ULSI of FFT. Communication présentée à 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS 2014), Marseille, France (p. 750-753). Tiré de https://doi.org/10.1109/ICECS.2014.7050094Communication de conférence Benyoussef, M., Boland, J.-F., Nicolescu, G., Bois, G. & Hugues, J. (2014). Design space exploration: bridging the gap between high-level models and virtual execution platforms. Communication présentée à Embedded Real Time System and Software Congress (ERTS2 2014), Toulouse, France (10 pages). Tiré de https://tel.archives-ouvertes.fr/ERTS2014/hal-02272408v1
- 2013
Communication de conférence Bois, G. (2013). A Complete HW/SW Codesign flow for heterogeneous platforms. Communication présentée à Workshop on Many-Core Embedded Systems (MCES2013), Montréal, Québec.Communication de conférence Bois, G. (2013). End-to-end automated HW/SW co-design for reconfigurable SoC. Communication présentée à Electronic Design Process Symposium (EDPS 2013), Monterey, Calif.Communication de conférence Vakili, S., Langlois, J.M.P. & Bois, G. (2013). Finite-precision error modeling using affine arithmetic. Communication présentée à 38th IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2013), Vancouver, BC, Canada (p. 2591-2595). Tiré de https://doi.org/10.1109/ICASSP.2013.6638124Communication de conférence Savard, J., Bao, L., Bois, G. & Boland, J.-F. (2013). Model-based design flow driven by integrated modular avionic simulations. Communication présentée à SAE AeroTech Congress and Exhibition (AEROTECH 2013), Montréal, Québec.
- 2012
Communication de conférence Moss, L., Guerard, H., Dare, G. & Bois, G. (2012). An ESL methodology for rapid creation of embedded aerospace systems using hardware-software co-design on virtual platforms. Communication présentée à SAE 2012 Aerospace Electronics and Avionics Systems Conference, Phoenix, AZ (10 pages). Tiré de https://doi.org/10.4271/2012-01-2133Communication de conférence Boland, J.-F., Bois, G. & Oudet, J.-P. (2012). Novel methodologies to support the architectural exploration of safety-critical systems. Communication présentée à Recherche et Innovation pour les Transports du Futur (RITF 2012), Paris, France.Communication de conférence Pollina, M., Leclerc, Y., Conquet, E., Bois, G. & Moss, L. (2012). The Assert Set of Tools for Engineering (TASTE): demonstrator, HW/SW codesign and future evolution. Communication présentée à Embedded Real Time Software and Systems (ERTS2 2012), Toulouse, France (4 pages).
- 2011
Communication de conférence Carmel-Veilleux, T., Boland, J.-F. & Bois, G. (2011). A novel low-overhead flexible instrumentation framework for virtual platforms. Communication présentée à 22nd IEEE International Symposium on Rapid System Prototyping (RSP 2011), Karlsruhe, Germany (p. 92-98). Tiré de https://doi.org/10.1109/RSP.2011.5929981Communication de conférence Vakili, S., Gil, D.C., Langlois, J.M.P., Savaria, Y. & Bois, G. (2011). Customized embedded processor design for global photographic tone mapping. Communication présentée à 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), Beirut, Lebanon (p. 382-385). Tiré de https://doi.org/10.1109/ICECS.2011.6122293Communication de conférence Le Beux, S., Trajkovic, J., O'Connor, I., Nicolescu, G., Bois, G. & Paulin, P. (2011). Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology. Communication présentée à 14th Design, Automation and Test in Europe Conference and Exhibition (DATE 2011), Grenoble, France (p. 788-793). Tiré de https://doi.org/10.1109/DATE.2011.5763134Communication de conférence Pollina, M., Leclerc, Y., Conquet, E., Perrotin, M., Bois, G. & Moss, L. (2011). The Assert Set of Tools for Engineering (TASTE): current features, demonstrator and future evolution. Communication présentée à DAta Systems In Aerospace (DASIA 2011), San Anton, Malta (5 pages). Tiré de http://articles.adsabs.harvard.edu/cgi-bin/nph-iarticle_query?2011ESASP.694E..37P&data_type=PDF_HIGH&whole_paper=YES&type=PRINTER&filetype=.pdf
- 2010
Communication de conférence Le Beux, S., Nicolescu, G., Bois, G. & Paulin, P. (2010). A system-level exploration flow for optical network on chip (ONoC) in 3D MPSoC. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France (p. 3613-3616). Tiré de https://doi.org/10.1109/ISCAS.2010.5537794Communication de conférence Rogers-Vallée, M., Cantin, M.-A., Moss, L. & Bois, G. (2010). IP characterization methodology for fast and accurate power consumption estimation at transactional level model. Communication présentée à IEEE International Conference on Computer Design (ICCD 2010), Amsterdam, Netherlands (p. 534-541). Tiré de https://doi.org/10.1109/ICCD.2010.5647622
- 2009
Communication de conférence Le Beux, S., Nicolescu, G., Bois, G., Bouchebaba, Y., Langevin, M. & Paulin, P. (2009). Optimizing configuration and application mapping for MPSoC architectures. Communication présentée à NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2009), San Francisco, California (p. 474-481). Tiré de https://doi.org/10.1109/AHS.2009.35
- 2008
Communication de conférence Fontaine, S., Goyette, S., Langlois, J.M.P. & Bois, G. (2008). Acceleration of a target tracking algo-rithm using an application specific instruction set processor. Communication présentée à IEEE International Conference on Computer Design (ICCD 2008). Tiré de https://doi.org/10.1109/ICCD.2008.4751870Communication de conférence Moss, L., Cantin, M.-A., Bois, G. & Aboulhamid, E.M. (2008). Automation of communication refinement and hardware synthesis within a system-level design methodology. Communication présentée à 19th IEEE/IFIP International Symposium on Rapid System Prototyping (p. 75-81). Tiré de https://doi.org/10.1109/RSP.2008.17Communication de conférence Fontaine, S., Filion, L. & Bois, G. (2008). Exploring ISS abstractions for embedded software design. Communication présentée à 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools (DSD 2008) (p. 651-655). Tiré de https://doi.org/10.1109/DSD.2008.59
- 2007
Communication de conférence Moss, L., De Nanclas, M., Filion, L., Fontaine, S., Bois, G. & Aboulhamid, M. (2007). Seamless hardware/software performance co-monitoring in a codesign simulation environment with RTOS support. Communication présentée à Design, Automation and Test in Europe Conference and Exhibition (DATE 2007), Nice Acropolis, France (p. 876-881). Tiré de https://doi.org/10.1109/DATE.2007.364403
- 2006
Communication de conférence Provost, S., Lavigueur, B., Bois, G. & Nicolescu, G. (2006). Integration of Configurable Processors in a Multiprocessor Platform. Communication présentée à IEEE International SOC Conference (SOCC 2006) (p. 221-224). Tiré de https://doi.org/10.1109/SOCC.2006.283885Communication de conférence Deslauriers, F., Langevin, M., Bois, G., Savaria, Y. & Paulin, P. (2006). RoC: a scalable network on chip based on the token ring concept. Communication présentée à 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), Gatineau, Que., Canada. Tiré de https://doi.org/10.1109/NEWCAS.2006.250915
- 2005
Communication de conférence Dubois, M., Savaria, Y. & Bois, G. (2005). A Generic Ahb Bus for Implementing High-Speed Locally Synchronous Islands. Communication présentée à IEEE SoutheastCon 2004, Fort Lauderdale, Florida, USA (p. 11-16). Tiré de https://doi.org/10.1109/SECON.2005.1423208Communication de conférence Thibeault, J.F., Hubin, M., Deslauriers, F., Samson, P. & Bois, G. (2005). A Reprogrammable Soc Design for a Real-Time Control Application. Communication présentée à IEEE International Conference on Microelectronic Systems Education (MSE 2005), Anaheim, California, USA (p. 73-74). Tiré de https://doi.org/10.1109/MSE.2005.11Communication de conférence Mahoney, P., Savaria, Y., Bois, G. & Plante, P. (2005). Parallel hashing memories : an alternative to content addressable memories. Communication présentée à 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), Québec City, Que., Canada (p. 223-226). Tiré de https://doi.org/10.1109/NEWCAS.2005.1496691
- 2004
Communication de conférence Quinn, D., Lavigueur, B., Bois, G. & Aboulhamid, M. (2004). A system level exploration platform and methodology for network applications based on configurable processors. Communication présentée à Design, Automation and Test in Europe Conference and Exhibition (DATE 2004), Paris, France (p. 364-369). Tiré de https://doi.org/10.1109/DATE.2004.1268874Communication de conférence Lapalme, J., Aboulhamid, E.M., Nicolescu, G., Charest, L., Boyer, F.R., David, J.P. & Bois, G. (2004). [dot]Net framework - A solution for the next generation tools for system-level modeling and simulation. Communication présentée à Design, Automation and Test in Europe Conference and Exhibition (DATE 2004), Paris, France (p. 732-733). Tiré de https://doi.org/10.1109/DATE.2004.1268952Communication de conférence Lapalme, J., Aboulhamed, E.M., Nicolescu, G., Charest, L., Boyer, F.R., David, J.P. & Bois, G. (2004). Esys.net: A New Solution for Embedded Systems Modeling and Simulation. Communication présentée à ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2004), Washington, D.C. (Publié dans ACM Sigplan Notices, 39(7), 107-114). Tiré de https://doi.org/10.1145/997163.997179Communication de conférence Benny, O., Rondonneau, M., Chevalier, J., Bois, G., Aboulhamid, E.M. & Boyer, F.-R. (2004). SoC software refinement approach for a systemC platform. Communication présentée à Design & Verification Conference & Exhibition (DVCon 2004), San Jose, California.Communication de conférence Chevalier, J., Benny, O., Rondonneau, M., Bois, G., Aboulhamid, E.M. & Boyer, F.R. (2004). Space: a Hardware/Software Systemc Modeling Platform Including an Rtos. Communication présentée à Forum on Specification and Design Languages (FDL 2003), Frankfurt, Germany (p. 91-104). Tiré de https://doi.org/10.1007/1-4020-7991-5_6Communication de conférence Regimbal, S., Savaria, Y. & Bois, G. (2004). Verification strategy determination using dependence analysis of transaction-level models. Communication présentée à 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Banff, Alta., Canada (p. 87-92). Tiré de https://doi.org/10.1109/IWSOC.2004.1319856
- 2003
Communication de conférence Bertola, M. & Bois, G. (2003). A methodology for the design of AHB bus master wrappers. Communication présentée à Euromicro Symposium on Digital System Design (p. 90-95). Tiré de https://doi.org/10.1109/DSD.2003.1231905Communication de conférence Regimbal, S., Lemire, J.F., Savaria, Y., Bois, G., Aboulhamid, M. & Baron, A. (2003). Aspect Partitioning for Hardware Verification Reuse. Communication présentée à System-on-Chip for Real-Time Applications (p. 51-60). Tiré de https://doi.org/10.1007/978-1-4615-0351-4_6Communication de conférence Regimbal, S., Lemire, J.-F., Savaria, Y., Bois, G., Aboulhamid, E.M. & Baron, A. (2003). Automating functional coverage analysis based on an executable specification. Communication présentée à 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (p. 228-234). Tiré de https://doi.org/10.1109/IWSOC.2003.1213040Communication de conférence Bissou, J.P., Dubois, M., Savaria, Y. & Bois, G. (2003). High-speed system bus for a SoC network processing platform. Communication présentée à 15th International Conference on Microelectronics (ICM 2003), Cairo, Egypt (p. 194-197). Tiré de https://doi.org/10.1109/ICM.2003.238564Communication de conférence Lemire, J.F., Aboulhamid, E.M., Savaria, Y., Bois, G. & Baron, A. (2003). Implementing e assertion checkers from an SDL executable specifications. Communication présentée à DVCON, San José, USA.Communication de conférence Bertola, M. & Bois, G. (2003). Teaching Bus Architectures With a Basic, Hands-on Soc Platform. Communication présentée à IEEE International Conference on Microelectronic Systems Education (MSE 2003) (p. 68-69). Tiré de https://doi.org/10.1109/MSE.2003.1205259Communication de conférence Filion, L., Chevalier, W., Bois, G. & Aboulhamid, E.A. (2003). The Syslib-Picasso Methodology for the Co-Design Specification Capture Phase. Communication présentée à System-on-Chip for Real-Time Applications (p. 183-192). Tiré de https://doi.org/10.1007/978-1-4615-0351-4_17
- 2001
Communication de conférence Heneault, Y., Filion, L., Bois, G. & Aboulhamid, E.M. (2001). A Fast Hardware Co-Specification and Co-Simulation Methodology Integrated in a H/S Co-Design Platform. Communication présentée à 13th International Conference on Microelectronics (ICM 2001) (p. 253-256). Tiré de https://doi.org/10.1109/ICM.2001.997658Communication de conférence Nekili, M., Savaria, Y. & Bois, G. (2001). Minimizing process-induced skew using elay tuning. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2001), Sydney, Australie (p. 426-429). Tiré de https://doi.org/10.1109/ISCAS.2001.922264
- 1999
Communication de conférence Le Chapelain, B., Mechain, A., Savaria, Y. & Bois, G. (1999). Development of a high performance TSPC library for implementation of large digital building blocks. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 1999), Orlando, FL, USA (p. 443-446). Tiré de https://doi.org/10.1109/ISCAS.1999.777908
- 1998
Communication de conférence Nekili, M., Savaria, Y., Bois, G., Bayoumi, M.A. & Jullien, G. (1998). Design of clock distribution networks in presence of process variations. Communication présentée à 8th Great Lakes Symposium on VLSI, Lafayette, LA, USA (p. 95-102). Tiré de https://doi.org/10.1109/GLSV.1998.665206Communication de conférence Shaditalab, M., Bois, G., Sawan, M., Pocek, K.L. & Arnold, J.M. (1998). Self-sorting radix-2 FFT on FPGAs using parallel pipelined distributed arithmetic blocks. Communication présentée à IEEE Symposium on FPGAs for Custom Computing Machines, Napa Valley, CA (p. 337-338). Tiré de https://doi.org/10.1109/FPGA.1998.707943
- 1997
Communication de conférence Bois, G., Bosi, B. & Savaria, Y. (1997). High performance reconfigurable coprocessor for digital signal processing. Communication présentée à 14th Annual International Conference of the Mentor Graphics Users' Group, Portland, Oregon.Communication de conférence Pera, F., Savaria, Y. & Bois, G. (1997). Time delay measurement methods for integrated transmission lines and high speed cells characterization. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 1997), Hong Kong, Hong Kong (p. 293-296). Tiré de https://doi.org/10.1109/ISCAS.1997.608710
- 1996
Communication de conférence Savaria, Y., Bois, G., Popovic, P. & Wayne, A. (1996). Computational acceleration methodologies: advantages of reconfigurable acceleration subsystems. Communication présentée à High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic (p. 195-205). Tiré de https://doi.org/10.1117/12.255817Communication de conférence Lejmi, S., Bois, G. & Savaria, Y. (1996). On the effects of retiming applied to self-checking sequential circuit. Communication présentée à 2nd IEEE On-Line Testing Workshop, Biarritz (p. 96-99).
- 1994
Communication de conférence Nekili, M., Savaria, Y. & Bois, G. (1994). A variable-size parallel regenerator for long integrated interconnections. Communication présentée à 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA (p. 50-53). Tiré de https://doi.org/10.1109/MWSCAS.1994.519188Communication de conférence Nekili, M., Savaria, Y. & Bois, G. (1994). Fast low-power driver for long interconnections in VLSI systems. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 1994), Londres (p. 343-346). Tiré de https://doi.org/10.1109/ISCAS.1994.409267Communication de conférence Kroumba, S.M., Bois, G. & Savaria, Y. (1994). Synthesis approach for the generation of parallel architectures. Communication présentée à 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), Lafayette, LA, USA (p. 323-326). Tiré de https://doi.org/10.1109/MWSCAS.1994.519249
- 2022
- Chapitres de livre (8)
- 2017
Chapitre de livre Jenn, E., Monteiro, F., Bois, G. & Duplantier, K. (2017). Design space exploration : the image based monitoring case. Dans Modelling and formal verification in action : the INGEQUIP Project Team.
- 2010
Chapitre de livre Bois, G., Moss, L., Filion, L. & Fontaine, S. (2010). Codesign experiences based on a virtual platform. Dans ESL models and their application : electronic system level design and verification practice (p. 273-309). Springer. Tiré de https://doi.org/10.1007/978-1-4419-0965-7_7
- 2009
Chapitre de livre Mahoney, P., Savaria, Y., Bois, G. & Plante, P. (2009). Performance characterization for the implementation of content addressable memories based on parallel hashing memories. Dans Transactions on High-Performance Embedded Architectures and Compilers. II (p. 307-325). Berlin, Germany: Springer. Tiré de https://doi.org/10.1007/978-3-642-00904-4_16Chapitre de livre Tsikhanovich, A., Aboulhamid, E.M. & Bois, G. (2009). Timing Specification in Transaction Level Models. Dans E.M. Aboulhamid & F. Rousseau (édit.), System Level Design with .Net Technology (p. 203-238). CRC Press. Tiré de https://www.taylorfrancis.com/books/9781439812129/chapters/10.1201/9781315218175-17
- 2004
Chapitre de livre Bois, G., Filion, L., Tsikhanovich, A. & Aboulhamid, E.M. (2004). Modélisation, raffinement et programmation orientée objet avec SystemC. Dans Spécification et validation des systèmes monopuces (p. 171-208). Lavoisier.Chapitre de livre Chevalier, J., Benny, O., Rondonneau, E.M. & Bois, G. (2004). SPACE : a hardware/software system C modeling platform including and RTOS. Dans Languages for system specification : selected contributions on UML, System C, System Verilog, Mixed-signal systems, and properties specification from FDL 2003 (p. 91-104). Springer. Tiré de https://doi.org/10.1007/1-4020-7991-5_6
- 2003
Chapitre de livre Charest, L., Aboulhamid, M. & Bois, G. (2003). Applying multi-paradigm and patterns approaches to hardware/software design and reuse. Dans Patterns and skeletons for parallel and distributed computing (p. 97-325). Springer. Tiré de https://doi.org/10.1007/978-1-4471-0097-3_11
- 1989
Chapitre de livre Cerny, E., Bois, G., Bourgault, M., Demers, L.-P., Fauvel, S., Jacques, P., Mailhot, P. & Roy, C. (1989). Integration of VLSI CAD tools based on cell-objects : the CHESHIRE system. Dans Progress in computer-aided VLSI Design : tools (Vol. 1).
- 2017
- Rapports (2)
- 2009
Rapport Moss, L. & Bois, G. (2009). On the Scott-continuity of tagged signal processes (Rapport n° EPM-RT-2009-01). École Polytechnique de Montréal. Tiré de https://publications.polymtl.ca/2640/
- 1994
Rapport Nekili, M., Bois, G. & Savaria, Y. (1994). Deterministic skew modeling and high-speed clocking of large integrated systems by using logic-based & hybrid H-trees (Rapport n° EPM-RT-94-09). École Polytechnique de Montréal.
- 2009
