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Article de revue (7) Communication de conférence (35) Livre Chapitre de livre (1) Brevet Rapport (1) Thèse Ensemble de données Ressource pédagogique Image Enregistrement audio Enregistrement vidéo Autre

François-Raymond Boyer (44)

  • Articles de revue (7)
    • 2019
      • Article de revue
        Benacer, I., Boyer, F.-R. & Savaria, Y. (2019). A High-Speed, Scalable, and Programmable Traffic Manager Architecture for Flow-Based Networking. IEEE Access, 7, 2231-2243. Tiré de https://doi.org/10.1109/ACCESS.2018.2886230
      • Article de revue
        Benacer, I., Boyer, F.-R. & Savaria, Y. (2019). HPQS: A Fast, High-Capacity, Hybrid Priority Queuing System for High-Speed Networking Devices. IEEE Access, 7, 130672-130684. Tiré de https://doi.org/10.1109/ACCESS.2019.2939154
    • 2018
      • Article de revue
        Benacer, I., Boyer, F.-R. & Savaria, Y. (2018). A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(10), 1939-1952. Tiré de https://doi.org/10.1109/TVLSI.2018.2838044
    • 2012
      • Article de revue
        Siadjine Njinowa, M., Tien Bui, H. & Boyer, F.-R. (2012). Novel Threshold-Based Standard-Cell Flash ADC. Circuits and Systems, 3(1), 29-34. Tiré de https://doi.org/10.4236/cs.2012.31005
    • 2011
      • Article de revue
        Hosseini, P., Martins, S., Martin, T., Radziszewski, P. & Boyer, F.-R. (2011). Acoustic emissions simulation of tumbling mills using charge dynamics. Minerals Engineering, 24(13), 1440-1447. Tiré de https://doi.org/10.1016/j.mineng.2011.07.002
    • 2006
      • Article de revue
        Boyer, F.R., Epassa, H.G. & Savaria, Y. (2006). Embedded power-aware cycle by cycle variable speed processor. IEE Proceedings. Computers and Digital Techniques, 153(4), 283-290. Tiré de https://doi.org/10.1049/ip-cdt:20050170
    • 2001
      • Article de revue
        Boyer, F.R., Aboulhamid, E.M., Savaria, Y. & Boyer, M. (2001). Optimal Design of Synchronous Circuits Using Software Pipelining Techniques. ACM Transactions on Design Automation of Electronic Systems, 6(4), 516-532. Tiré de https://doi.org/10.1145/502175.502180
  • Communications de conférence (35)
    • 2019
      • Communication de conférence
        Santiago Da Silva, J., Boyer, F.-R. & Langlois, J.M.P. (2019). Module-per-object: A human-driven methodology for c++-based high-level synthesis design. Communication présentée à 27th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2019), San Diego, CA, United states (p. 218-226). Tiré de https://doi.org/10.1109/FCCM.2019.00037
    • 2018
      • Communication de conférence
        Benacer, I., Boyer, F.-R. & Savaria, Y. (2018). Design of a low latency 40 Gb/s flow-based traffic manager using high-level synthesis. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy (5 pages). Tiré de https://doi.org/10.1109/ISCAS.2018.8351332
      • Communication de conférence
        Santiago da Silva, J., Boyer, F.-R., Chiquette, L.-O. & Langlois, J.M.P. (2018). Extern objects in P4: an ROHC compressing scheme case study. Communication présentée à IEEE Conference on Network Softwarization (NetSoft 2018), Montréal, Québec. Tiré de https://doi.org/10.1109/NETSOFT.2018.8460108
      • Communication de conférence
        Benacer, I., Boyer, F.-R. & Savaria, Y. (2018). HPQ: a high capacity hybrid priority queue architecture for high-speed network switches. Communication présentée à 16th IEEE International New Circuits and Systems Conference (NEWCAS 2018), Montréal, Québec (p. 229-233). Tiré de https://doi.org/10.1109/NEWCAS.2018.8585434
      • Communication de conférence
        Santiago da Silva, J., Boyer, F.-R. & Langlois, J.M.P. (2018). P4-compatible high-level synthesis of low latency 100 Gb/s streaming packet parsers in FPGAs. Communication présentée à ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2018), Monterey, California, USA (p. 147-152). Tiré de https://doi.org/10.1145/3174243.3174270
    • 2017
      • Communication de conférence
        Benacer, I., Boyer, F.-R. & Savaria, Y. (2017). A high-speed traffic manager architecture for flow-based networking. Communication présentée à 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France (p. 161-164). Tiré de https://doi.org/10.1109/NEWCAS.2017.8010130
    • 2016
      • Communication de conférence
        Benacer, I., Boyer, F.-R., Bélanger, N. & Savaria, Y. (2016). A fast systolic priority queue architecture for a flow-based Traffic Manager. Communication présentée à 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages). Tiré de https://doi.org/10.1109/NEWCAS.2016.7604761
      • Communication de conférence
        Lacroix, A.B., Langlois, J.M.P., Boyer, F.-R., Gosselin, A. & Bois, G. (2016). Node configuration for the Aho-Corasick algorithm in intrusion detection systems. Communication présentée à 12th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2016), Santa Clara, California (p. 121-122). Tiré de https://doi.org/10.1145/2881025.2889473
      • Communication de conférence
        Alizadeh, R., Belanger, N., Savaria, Y. & Boyer, F.R. (2016). Performance characterization of an SCMA decoder. Communication présentée à 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages). Tiré de https://doi.org/10.1109/NEWCAS.2016.7604820
    • 2013
      • Communication de conférence
        Njinowa, M.S., Bui, H.T. & Boyer, F.-R. (2013). Design of low power 4-bit flash ADC based on standard cells. Communication présentée à 11th IEEE International New Circuits and Systems Conference (NEWCAS 2013), Paris, France (4 pages). Tiré de https://doi.org/10.1109/NEWCAS.2013.6573626
    • 2010
      • Communication de conférence
        Njinowa, M.S., Bui, H.T. & Boyer, F.-R. (2010). Peak-to-peak jitter reduction technique for the Free-Running Period Synthesizer (FRPS). Communication présentée à IEEE International Symposium on Circuits and Systems. ISCAS 2010, Paris, France (p. 1312-1315). Tiré de https://doi.org/10.1109/ISCAS.2010.5537254
    • 2009
      • Communication de conférence
        Njinowa, M.S., Bui, H.T. & Boyer, F.-R. (2009). Design and optimization of a low complexity all-digital digital-to-analog converter. Communication présentée à Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France. Tiré de https://doi.org/10.1109/NEWCAS.2009.5290413
      • Communication de conférence
        Vezant, B., Mansuy, C., Bui, H.T. & Boyer, F.-R. (2009). Direct digital synthesis-based all-digital phase-locked loop. Communication présentée à Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France (p. 43-46). Tiré de https://doi.org/10.1109/NEWCAS.2009.5290469
      • Communication de conférence
        Trabelisi, A., Boyer, F.R. & Boukadoum, M. (2009). Robust Estimation of LP Parameters in White Noise with Unknown Variance. Communication présentée à 16th IEEE International Conference on Electronics, Circuits and Systems, Medina, Tunisia (p. 335-338). Tiré de https://doi.org/10.1109/ICECS.2009.5411004
    • 2008
      • Communication de conférence
        Pontikakis, B., Bui, H.T., Boyer, F.-R. & Savaria, Y. (2008). A novel phase-locked loop (PLL) architecture without an analog loop filter for better integration in ultra-deep submicron SoCs. Communication présentée à Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008) (p. 363-366). Tiré de https://doi.org/10.1109/NEWCAS.2008.4606396
    • 2007
      • Communication de conférence
        Pontikakis, B., Bui, H.T., Boyer, F.-R. & Savaria, Y. (2007). A low-complexity high-speed clock generator for dynamic frequency scaling of FPGA and standard-cell based designs. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, Louisiana (p. 633-636). Tiré de https://doi.org/10.1109/ISCAS.2007.378817
      • Communication de conférence
        Trabelisi, A., Boyer, F.R., Savaria, Y. & Boukadoum, M. (2007). Improving LPC Analysis of Speech in Additive Noise. Communication présentée à IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Québec (p. 93-96). Tiré de https://doi.org/10.1109/NEWCAS.2007.4487956
      • Communication de conférence
        Trabelisi, A., Boyer, F.R., Savaria, Y. & Boukadoum, M. (2007). Iterative Noise-Compensated Method to Improve LPC Based Speech Analysis. Communication présentée à 14h IEEE International Conference on Electronics, Circuits & Systems, Marrakech, Morocco (p. 1364-1367). Tiré de https://doi.org/10.1109/ICECS.2007.4511252
      • Communication de conférence
        Pontikakis, B., Boyer, F.-R., Savaria, Y. & Bui, H.T. (2007). Precise free-running period synthesizer (FRPS) with process and temperature compensation. Communication présentée à 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007) (p. 1118-1121). Tiré de https://doi.org/10.1109/MWSCAS.2007.4488754
      • Communication de conférence
        Trabelsi, A., Boyer, F.R. & Savaria, Y. (2007). Speech enhancement based noise PSD estimator to remove cosine shaped residual noise. Communication présentée à 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007) (p. 393-396). Tiré de https://doi.org/10.1109/MWSCAS.2007.4488613
    • 2006
      • Communication de conférence
        Pontikakis, B., Boyer, F.-R. & Savaria, Y. (2006). A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece (p. 1259-1262). Tiré de https://doi.org/10.1109/ISCAS.2006.1692821
    • 2005
      • Communication de conférence
        Epassa, H.G., Boyer, F.R. & Savaria, Y. (2005). Implementation of a Cycle by Cycle Variable Speed Processor. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan (p. 3335-3338). Tiré de https://doi.org/10.1109/ISCAS.2005.1465342
      • Communication de conférence
        Pontikakis, B., Boyer, F.R. & Savaria, Y. (2005). Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period. Communication présentée à 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005), Banff, Alberta, Canada (p. 454-458). Tiré de https://doi.org/10.1109/IWSOC.2005.90
    • 2004
      • Communication de conférence
        Boyer, F.-R., Epassa, H.G., Pontikakis, B., Savaria, Y. & Ling, W. (2004). A variable period clock synthesis (VPCS) architecture for next-generation power-aware SoC applications. Communication présentée à 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec (p. 145-148). Tiré de https://doi.org/10.1109/NEWCAS.2004.1359043
      • Communication de conférence
        Lapalme, J., Aboulhamid, E.M., Nicolescu, G., Charest, L., Boyer, F.R., David, J.P. & Bois, G. (2004). [dot]Net framework - A solution for the next generation tools for system-level modeling and simulation. Communication présentée à Design, Automation and Test in Europe Conference and Exhibition (DATE 2004), Paris, France (p. 732-733). Tiré de https://doi.org/10.1109/DATE.2004.1268952
      • Communication de conférence
        Lapalme, J., Aboulhamed, E.M., Nicolescu, G., Charest, L., Boyer, F.R., David, J.P. & Bois, G. (2004). Esys.net: A New Solution for Embedded Systems Modeling and Simulation. Communication présentée à ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2004), Washington, D.C. (Publié dans ACM Sigplan Notices, 39(7), 107-114). Tiré de https://doi.org/10.1145/997163.997179
      • Communication de conférence
        Benny, O., Rondonneau, M., Chevalier, J., Bois, G., Aboulhamid, E.M. & Boyer, F.-R. (2004). SoC software refinement approach for a systemC platform. Communication présentée à Design & Verification Conference & Exhibition (DVCon 2004), San Jose, California.
      • Communication de conférence
        Chevalier, J., Benny, O., Rondonneau, M., Bois, G., Aboulhamid, E.M. & Boyer, F.R. (2004). Space: a Hardware/Software Systemc Modeling Platform Including an Rtos. Communication présentée à Forum on Specification and Design Languages (FDL 2003), Frankfurt, Germany (p. 91-104). Tiré de https://doi.org/10.1007/1-4020-7991-5_6
    • 2003
      • Communication de conférence
        Boyer, F.R., Yang, L., Aboulamid, E.M., Charest, L. & Nicolescu, G. (2003). Multiple SimpleScalar Processors with Introspection, under SystemC. Communication présentée à 46th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2003), Cairo, Egypt (p. 1400-1404). Tiré de https://doi.org/10.1109/MWSCAS.2003.1562557
    • 2002
      • Communication de conférence
        Li, J., Boyer, F.R. & Aboulhamid, E.M. (2002). Retargetable C Compiler for Network Processors. Communication présentée à 6th World Multiconference on Systemics, Cybernetics and Informatics, Orlando, Florida (p. 445-448).
    • 2001
      • Communication de conférence
        Boyer, F.-R., Aboulhamid, E.M. & Savaria, Y. (2001). Minimizing sensitivity to clock skew variations using level sensitive latches. Communication présentée à 15th European Conference on Circuit Theory and Design (ECCTD 2001), Espoo, Finland.
      • Communication de conférence
        Martins, S., Hosseini, P., Martin, T., Radziszewski, P., Boyer, F.R., Faucher, A., Makni, S. & Sabih, A. (2001). Simulating tumbling mill acoustic signals using DEM. Communication présentée à 5th International Conference on Autogenous and Semiautogenous Grinding Technology (SAG 2011), Vancouver, B.C.
    • 2000
      • Communication de conférence
        Boyer, F.-R., Aboulhamid, E.M. & Savaria, Y. (2000). Efficient verification method for a class of multi-phase sequential circuits. Communication présentée à 7th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2000) (p. 510-515). Tiré de https://doi.org/10.1109/ICECS.2000.911590
    • 1998
      • Communication de conférence
        Boyer, F.-R., Aboulhamid, E.M., Savaria, Y. & Bennour, I.E. (1998). Optimal design of synchronous circuits using software pipelining techniques. Communication présentée à International Conference on Computer Design. VLSI in Computers and Processors, Austin, Texas (p. 62-67). Tiré de https://doi.org/10.1109/ICCD.1998.727024
    • 1996
      • Communication de conférence
        Cloutier, J., Cosatto, E., Pigeon, S., Boyer, F.-R. & Simard, G. (1996). VIP: an FPGA-based processor for image processing and neural networks. Communication présentée à 5th International Conference on Microelectronics for Neural Networks, Lausanne, Switzerland (p. 330-336). Tiré de https://doi.org/10.1109/MNNFS.1996.493811
  • Chapitres de livre (1)
    • 2012
      • Chapitre de livre
        Abdelaziz, T., Boyer, F.R. & Savaria, Y. (2012). Real-time dual-microphone speech enhancement. Dans Speech enhancement, modeling and recognition - algorithms and applications (p. 19-34). Tiré de https://doi.org/10.5772/35869
  • Rapports (1)
    • 2006
      • Rapport
        Trabelsi, A., Boyer, F.-R. & Savaria, Y. (2006). On the application of minimum noise tracking to cancel cosine shaped residual noise (Rapport n° EPM-RT-2006-09). École Polytechnique de Montréal. Tiré de https://publications.polymtl.ca/3157/