Répertoire des expertises

Vous êtes ici

Publications par type

Article de revue (4) Communication de conférence (25) Livre Chapitre de livre Brevet Rapport (1) Thèse

François-Raymond Boyer (30)

  • Articles de revue (4)
    • 2011
      • Article de revue
        Hosseini, P., Martins, S., Martin, T., Radziszewski, P. & Boyer, F.-R. (2011). Acoustic emissions simulation of tumbling mills using charge dynamics. Minerals Engineering, 24(13), 1440-1447.
    • 2006
      • Article de revue
        Boyer, F.R., Epassa, H.G. & Savaria, Y. (2006). Embedded power-aware cycle by cycle variable speed processor. IEE Proceedings. Computers and Digital Techniques, 153(4), 283-290.
    • 2004
      • Article de revue
        Lapalme, J., Aboulhamed, E.M., Nicolescu, G., Charest, L., Boyer, F.R., David, J.P. & Bois, G. (2004). Esys.net: A New Solution for Embedded Systems Modeling and Simulation. ACM Sigplan Notices, 39(7), 107-114. Tiré de https://doi.org/10.1145/997163.997179
    • 2001
      • Article de revue
        Boyer, F.R., Aboulhamid, E.M., Savaria, Y. & Boyer, M. (2001). Optimal Design of Synchronous Circuits Using Software Pipelining Techniques. ACM Transactions on Design Automation of Electronic Systems, 6(4), 516-532.
  • Communications de conférence (25)
    • 2018
      • Communication de conférence
        Benacer, I., Boyer, F.-R. & Savaria, Y. (2018). Design of a low latency 40 Gb/s flow-based traffic manager using high-level synthesis. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy (5 pages). Tiré de https://doi.org/10.1109/ISCAS.2018.8351332
      • Communication de conférence
        Santiago da Silva, J., Boyer, F.-R., Chiquette, L.-O. & Langlois, J.M.P. (2018). Extern objects in P4: an ROHC compressing scheme case study. Communication présentée à IEEE Conference on Network Softwarization (NetSoft 2018), Montréal, QC.
      • Communication de conférence
        Santiago da Silva, J., Boyer, F.-R. & Langlois, J.M.P. (2018). P4-compatible high-level synthesis of low latency 100 Gb/s streaming packet parsers in FPGAs. Communication présentée à ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2018), Monterey, California, USA (p. 147-152). Tiré de https://doi.org/10.1145/3174243.3174270
    • 2017
      • Communication de conférence
        Benacer, I., Boyer, F.-R. & Savaria, Y. (2017). A high-speed traffic manager architecture for flow-based networking. Communication présentée à 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France (p. 161-164). Tiré de https://doi.org/10.1109/NEWCAS.2017.8010130
    • 2016
      • Communication de conférence
        Benacer, I., Boyer, F.-R., Bélanger, N. & Savaria, Y. (2016). A fast systolic priority queue architecture for a flow-based Traffic Manager. Communication présentée à 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages). Tiré de https://doi.org/10.1109/NEWCAS.2016.7604761
      • Communication de conférence
        Lacroix, A.B., Langlois, J.M.P., Boyer, F.-R., Gosselin, A. & Bois, G. (2016). Node configuration for the Aho-Corasick algorithm in intrusion detection systems. Communication présentée à 12th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2016), Santa Clara, California (p. 121-122). Tiré de https://doi.org/10.1145/2881025.2889473
      • Communication de conférence
        Alizadeh, R., Belanger, N., Savaria, Y. & Boyer, F.R. (2016). Performance characterization of an SCMA decoder. Communication présentée à 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages). Tiré de https://doi.org/10.1109/NEWCAS.2016.7604820
    • 2010
      • Communication de conférence
        Njinowa, M.S., Bui, H.T. & Boyer, F.-R. (2010). Peak-to-peak jitter reduction technique for the Free-Running Period Synthesizer (FRPS). Communication présentée à IEEE International Symposium on Circuits and Systems. ISCAS 2010, Paris, France (p. 1312-1315).
    • 2009
      • Communication de conférence
        Njinowa, M.S., Bui, H.T. & Boyer, F.-R. (2009). Design and optimization of a low complexity all-digital digital-to-analog converter. Communication présentée à Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France.
      • Communication de conférence
        Vezant, B., Mansuy, C., Bui, H.T. & Boyer, F.-R. (2009). Direct digital synthesis-based all-digital phase-locked loop. Communication présentée à Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France (p. 43-46).
      • Communication de conférence
        Trabelisi, A., Boyer, F.R. & Boukadoum, M. (2009). Robust Estimation of LP Parameters in White Noise with Unknown Variance. Communication présentée à 16th IEEE International Conference on Electronics, Circuits and Systems, Medina, Tunisia (p. 335-338).
    • 2008
      • Communication de conférence
        Pontikakis, B., Bui, H.T., Boyer, F.-R. & Savaria, Y. (2008). A novel phase-locked loop (PLL) architecture without an analog loop filter for better integration in ultra-deep submicron SoCs. Communication présentée à Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008) (p. 363-366).
    • 2007
      • Communication de conférence
        Pontikakis, B., Bui, H.T., Boyer, F.-R. & Savaria, Y. (2007). A low-complexity high-speed clock generator for dynamic frequency scaling of FPGA and standard-cell based designs. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, LA, United States (p. 633-636).
      • Communication de conférence
        Trabelisi, A., Boyer, F.R., Savaria, Y. & Boukadoum, M. (2007). Improving LPC Analysis of Speech in Additive Noise. Communication présentée à IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Canada (p. 93-96).
      • Communication de conférence
        Trabelisi, A., Boyer, F.R., Savaria, Y. & Boukadoum, M. (2007). Iterative Noise-Compensated Method to Improve LPC Based Speech Analysis. Communication présentée à 14h IEEE International Conference on Electronics, Circuits & Systems, Marrakech, Morocco (p. 1364-1367).
      • Communication de conférence
        Pontikakis, B., Boyer, F.-R., Savaria, Y. & Bui, H.T. (2007). Precise free-running period synthesizer (FRPS) with process and temperature compensation. Communication présentée à 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007) (p. 1118-1121).
      • Communication de conférence
        Trabelsi, A., Boyer, F.R. & Savaria, Y. (2007). Speech enhancement based noise PSD estimator to remove cosine shaped residual noise. Communication présentée à 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007) (p. 393-396).
    • 2006
      • Communication de conférence
        Pontikakis, B., Boyer, F.-R. & Savaria, Y. (2006). A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece (p. 1259-1262).
    • 2005
      • Communication de conférence
        Epassa, H.G., Boyer, F.R. & Savaria, Y. (2005). Implementation of a Cycle by Cycle Variable Speed Processor. Communication présentée à IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan (p. 3335-3338).
      • Communication de conférence
        Pontikakis, B., Boyer, F.R. & Savaria, Y. (2005). Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period. Communication présentée à 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005), Banff, Alberta, Canada (p. 454-458).
    • 2004
      • Communication de conférence
        Boyer, F.-R., Epassa, H.G., Pontikakis, B., Savaria, Y. & Ling, W. (2004). A variable period clock synthesis (VPCS) architecture for next-generation power-aware SoC applications. Communication présentée à 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal (p. 145-148).
      • Communication de conférence
        Lapalme, J., Aboulhamid, E.M., Nicolescu, G., Charest, L., Boyer, F.R., David, J.P. & Bois, G. (2004). Robust Estimation of LP Parameters in White Noise with Unknown Variance. Communication présentée à Design, Automation and Test in Europe Conference and Exhibition (DATE 2004), Paris, France (p. 732-733).
      • Communication de conférence
        Chevalier, J., Benny, O., Rondonneau, M., Bois, G., Aboulhamid, E.M. & Boyer, F.R. (2004). Space: a Hardware/Software Systemc Modeling Platform Including an Rtos. Communication présentée à Forum on Specification and Design Languages (FDL 2003) (p. 91-104).
    • 2003
      • Communication de conférence
        Boyer, F.R., Yang, L., Aboulamid, E.M., Charest, L. & Nicolescu, G. (2003). Multiple SimpleScalar Processors with Introspection, under SystemC. Communication présentée à 46th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2003), Cairo, Egypt (p. 1400-1404).
    • 2002
      • Communication de conférence
        Li, J., Boyer, F.R. & Aboulhamid, E.M. (2002). Retargetable C Compiler for Network Processors. Communication présentée à 6th World Multiconference on Systemics, Cybernetics and Informatics, Orlando, Florida (p. 445-448).
  • Rapports (1)
    • 2006
      • Rapport
        Trabelsi, A., Boyer, F.-R. & Savaria, Y. (2006). On the application of minimum noise tracking to cancel cosine shaped residual noise (Rapport n° EPM-RT-2006-09). École Polytechnique de Montréal. Tiré de https://publications.polymtl.ca/3157/