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          François-Raymond
         Boyer

François-Raymond Boyer

Assistant Professor
Department of Computer Engineering

Publications

The bibliographic data is imported from Polytechnique Montréal's Directory of Publications. The bibliography below includes a majority of publications written by a professor/researcher affiliated with Polytechnique, since 1994 (if applicable). Publications before the professor's/researcher's affiliation with Polytechnique or before 1994 may also be included in this list. You may also consult the Directory of Scientific & Technical Publications for more information about the document type coverage.

1 A.B. Lacroix, J.M.P. Langlois, F.-R. Boyer, A. Gosselin, G. Bois (2016). Node configuration for the Aho-Corasick algorithm in Intrusion Detection Systems12th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2016), p. 121-122. DOI : 10.1145/2881025.2889473 
2 R. Alizadeh, N. Belanger, Y. Savaria, F.R. Boyer (2016). Performance characterization of an SCMA decoder14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), 4 pages. DOI : 10.1109/NEWCAS.2016.7604820 
3 I. Benacer, F.-R. Boyer, N. Bélanger, Y. Savaria (2016). A fast systolic priority queue architecture for a flow-based Traffic Manager14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), 4 pages. DOI : 10.1109/NEWCAS.2016.7604761 
4 P. Hosseini, S. Martins, T. Martin, P. Radziszewski, F.-R. Boyer (2011). Acoustic emissions simulation of tumbling mills using charge dynamics. Minerals Engineering, 24(13), p. 1440-1447.
5 M.S. Njinowa, H.T. Bui, F.-R. Boyer (2010). Peak-to-peak jitter reduction technique for the Free-Running Period Synthesizer (FRPS). IEEE International Symposium on Circuits and Systems. ISCAS 2010, p. 1312-1315.
6 B. Vezant, C. Mansuy, H.T. Bui, F.-R. Boyer (2009). Direct digital synthesis-based all-digital phase-locked loop. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), p. 43-46.
7 A. Trabelisi, F.R. Boyer, M. Boukadoum (2009). Robust Estimation of LP Parameters in White Noise with Unknown Variance. 16th IEEE International Conference on Electronics, Circuits and Systems, p. 335-338.
8 M.S. Njinowa, H.T. Bui, F.-R. Boyer (2009). Design and optimization of a low complexity all-digital digital-to-analog converter. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009).
9 B. Pontikakis, H.T. Bui, F.-R. Boyer, Y. Savaria (2008). A novel phase-locked loop (PLL) architecture without an analog loop filter for better integration in ultra-deep submicron SoCs. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), p. 363-366.
10 A. Trabelsi, F.R. Boyer, Y. Savaria (2007). Speech enhancement based noise PSD estimator to remove cosine shaped residual noise. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007), p. 393-396.
11 A. Trabelisi, F.R. Boyer, Y. Savaria, M. Boukadoum (2007). Improving LPC Analysis of Speech in Additive Noise. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), p. 93-96.
12 A. Trabelisi, F.R. Boyer, Y. Savaria, M. Boukadoum (2007). Iterative Noise-Compensated Method to Improve LPC Based Speech Analysis. 14h IEEE International Conference on Electronics, Circuits & Systems, p. 1364-1367.
13 B. Pontikakis, H.T. Bui, F.-R. Boyer, Y. Savaria (2007). A low-complexity high-speed clock generator for dynamic frequency scaling of FPGA and standard-cell based designs. IEEE International Symposium on Circuits and Systems (ISCAS 2007), p. 633-636.
14 B. Pontikakis, F.-R. Boyer, Y. Savaria, H.T. Bui (2007). Precise free-running period synthesizer (FRPS) with process and temperature compensation. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007), p. 1118-1121.
15 A. Trabelsi, F.-R. Boyer, Y. Savaria (2006). On the application of minimum noise tracking to cancel cosine shaped residual noise(Rapport 2006-09). 23 pages.
16 B. Pontikakis, F.-R. Boyer, Y. Savaria (2006). A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs. IEEE International Symposium on Circuits and Systems (ISCAS 2006), p. 1259-1262.
17 F.R. Boyer, H.G. Epassa, Y. Savaria (2006). Embedded power-aware cycle by cycle variable speed processor. IEE Proceedings. Computers and Digital Techniques, 153(4), p. 283-290.
18 B. Pontikakis, F.R. Boyer, Y. Savaria (2005). Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period. 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005), p. 454-458.
19 H.G. Epassa, F.R. Boyer, Y. Savaria (2005). Implementation of a Cycle by Cycle Variable Speed Processor. IEEE International Symposium on Circuits and Systems (ISCAS 2005), v. 4, p. 3335-3338.
20 J. Lapalme, E.M. Aboulhamid, G. Nicolescu, L. Charest, F.R. Boyer, J.P. David, G. Bois (2004). Robust Estimation of LP Parameters in White Noise with Unknown Variance. Design, Automation and Test in Europe Conference and Exhibition (DATE 2004), p. 732-733.
21 J. Lapalme, E.M. Aboulhamed, G. Nicolescu, L. Charest, F.R. Boyer, J.P. David, G. Bois (2004). Esys.net: A New Solution for Embedded Systems Modeling and SimulationACM Sigplan Notices, 39(7), p. 107-114. DOI : 10.1145/997163.997179 
22 J. Chevalier, O. Benny, M. Rondonneau, G. Bois, E.M. Aboulhamid, F.R. Boyer (2004). Space: a Hardware/Software Systemc Modeling Platform Including an Rtos. Forum on Specification and Design Languages (FDL 2003), p. 91-104.
23 F.-R. Boyer, H.G. Epassa, B. Pontikakis, Y. Savaria, W. Ling (2004). A variable period clock synthesis (VPCS) architecture for next-generation power-aware SoC applications. 2nd Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), p. 145-148.
24 F.R. Boyer, L. Yang, E.M. Aboulamid, L. Charest, G. Nicolescu (2003). Multiple SimpleScalar Processors with Introspection, under SystemC. 46th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2003), p. 1400-1404.
25 J. Li, F.R. Boyer, E.M. Aboulhamid (2002). Retargetable C Compiler for Network Processors. 6th World Multiconference on Systemics, Cybernetics and Informatics, p. 445-448.
26 F.R. Boyer, E.M. Aboulhamid, Y. Savaria, M. Boyer (2001). Optimal Design of Synchronous Circuits Using Software Pipelining Techniques. ACM Transactions on Design Automation of Electronic Systems, 6(4), p. 516-532.

 

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