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Directory of Expertises

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Yvon Savaria

Professor and Director
Department of Electrical Engineering

Publications

The bibliographic data is imported from Polytechnique Montréal's Directory of Publications. The bibliography below includes a majority of publications written by a professor/researcher affiliated with Polytechnique, since 1994 (if applicable). Publications before the professor's/researcher's affiliation with Polytechnique or before 1994 may also be included in this list. You may also consult the Directory of Scientific & Technical Publications for more information about the document type coverage.

1 T. Luinaud, Y. Savaria, J.M.P. Langlois (2017). An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only)ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2017), p. 287-288. DOI : 10.1145/3020078.3021770 
2 K.A. Hoque, O. Ait Mohamed, Y. Savaria (2017). Formal analysis of SEU mitigation for early dependability and performability analysis of FPGA-based space applicationsJournal of Applied Logic.  DOI : 10.1016/j.jal.2017.03.001 
3 G. Kazma, G.B. Hamad, O.A. Mohamed, Y. Savaria (2017). Analysis of SEU Propagation in Combinational Circuits at RTL Based on Satisfiability Modulo TheoriesGreat Lakes Symposium on VLSI (GLSVLSI 2017), p. 239-244. DOI : 10.1145/3060403.3060438 
4 F. Siaka, M. Akbarniai Tehrani, J.J. Laurin, Y. Savaria (2017). Radar system with enhanced angular resolution based on a novel frequency scanning reflector antennaIET Radar, Sonar & Navigation, 11(2), p. 350-358. DOI : 10.1049/iet-rsn.2016.0320 
5 T. Stimpfling, N. Bélanger, O. Cherkaoui, A. Béliveau, L. Béliveau, Y. Savaria (2017). Extensions to decision-tree based packet classification algorithms to address new classification paradigmsComputer Networks, 122, p. 83-95. DOI : 10.1016/j.comnet.2017.04.021 
6 T. Luinaud, Y. Savaria, J.M.P. Langlois (2017). An FPGA Coarse Grained Intermediate Fabric for Regular Expression SearchGreat Lakes Symposium on VLSI (GLSVLSI 2017), p. 423-426. DOI : 10.1145/3060403.3060429 
7 S. Vakili, J.M.P. Langlois, B. Boughzala, Y. Savaria (2016). Memory-Efficient String Matching for Intrusion Detection Systems using a High-Precision Pattern Grouping Algorithm12th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2016), p. 37-42. DOI : 10.1145/2881025.2881031 
8 A. Lakhssassi, R. Palenychka, Y. Savaria, M. Sayde, M. Zaremba (2016). Monitoring thermal stress in wafer-scale integrated circuits by the attentive vision method using an infrared cameraIEEE Transactions on Circuits and Systems for Video Technology, 26(2), p. 412-424. DOI : 10.1109/TCSVT.2015.2409632 
9 M.A. Tehrani, Y. Savaria, J.J. Laurin (2016). Multiple targets direction-of-arrival estimation in frequency scanning array antennasIET Radar, Sonar and Navigation, 10(3), p. 624-631. DOI : 10.1049/iet-rsn.2015.0401 
10 W. Hussain, O. Valorge, Y. Blaquiere, Y. Savaria (2016). A novel spatially configurable differential interface for an electronic system prototyping platformIntegration, the VLSI Journal, 55, p. 129-137. DOI : 10.1016/j.vlsi.2016.04.008 
11 O.A.T. Hasib, Y. Savaria, C. Thibeault (2016). WeSPer: a flexible small delay defect quality metric34th IEEE VLSI Test Symposium (VTS 2016), 6 pages. DOI : 10.1109/VTS.2016.7477266 
12 K.A. Hoque, O.A. Mohamed, Y. Savaria (2016). Applying formal verification to early assessment of FPGA-based aerospace applications: Methodology and experienceAnnual IEEE Systems Conference (SysCon 2016), 6 pages. DOI : 10.1109/SYSCON.2016.7490557 
13 W. Hussain, H. Fakhoury, P. Desgreys, Y. Blaquiere, Y. Savaria (2016). An asynchronous delta-modulator based A/D converter for an electronic system prototyping platformIEEE Transactions on Circuits and Systems I: Regular Papers, 63(6), p. 751-762. DOI : 10.1109/tcsi.2016.2538019 
14 M. Khelifi, D. Massicotte, Y. Savaria (2016). Towards efficient and concurrent FFTs implementation on Intel Xeon/MIC clusters for LTE and HPCIEEE International Symposium on Circuits and Systems (ISCAS 2016), p. 2611-2614. DOI : 10.1109/ISCAS.2016.7539128 
15 G.B. Hamad, O.A. Mohamed, Y. Savaria (2016). Towards formal abstraction, modeling, and analysis of single event transients at RTLIEEE International Symposium on Circuits and Systems (ISCAS 2016), p. 2166-2169. DOI : 10.1109/ISCAS.2016.7539010 
16 M. Fiorentino, Y. Savaria, C. Thibeault, P. Gervais (2016). A practical design method for prototyping self-timed processors using FPGAsIEEE International Symposium on Circuits and Systems (ISCAS 2015), p. 1754-1757. DOI : 10.1109/ISCAS.2016.7538907 
17 W. Hussain, Y. Savaria, Y. Blaquiere (2016). A compact spatially configurable differential input stage for a field programmable interconnection networkIEEE International Symposium on Circuits and Systems (ISCAS 2016), p. 313-316. DOI : 10.1109/ISCAS.2016.7527233 
18 A. Hassan, A. Trigui, U. Shafique, Y. Savaria, M. Sawan (2016). Wireless power transfer through metallic barriers enclosing a harsh environment, feasibility and preliminary resultsIEEE International Symposium on Circuits and Systems (ISCAS 2016), p. 2391-2394. DOI : 10.1109/ISCAS.2016.7539073 
19 G.B. Hamad, G. Kazma, O.A. Mohamed, Y. Savaria (2016). Efficient and accurate analysis of single event transients propagation using SMT-based techniques35th International Conference on Computer-Aided Design (ICCAD 2016), 7 pages. DOI : 10.1145/2966986.2967027 
20 F.Z. Tazi, C. Thibeault, Y. Savaria (2016). Detailed analysis of radiation-induced delays on I/O blocks of an SRAM-based FPGAIEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2016), 5 pages. DOI : 10.1109/CCECE.2016.7726600 
21 A. Trigui, M. Ali, A.C. Ammari, Y. Savaria, M. Sawan (2016). Quad-Level Carrier Width Modulation demodulator for micro-implants14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), 4 pages. DOI : 10.1109/NEWCAS.2016.7604801 
22 R. Alizadeh, N. Belanger, Y. Savaria, F.R. Boyer (2016). Performance characterization of an SCMA decoder14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), 4 pages. DOI : 10.1109/NEWCAS.2016.7604820 
23 I. Benacer, F.-R. Boyer, N. Bélanger, Y. Savaria (2016). A fast systolic priority queue architecture for a flow-based Traffic Manager14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), 4 pages. DOI : 10.1109/NEWCAS.2016.7604761 
24 M. Gémieux, Y. Savaria, G. Zhu, J.-F. Frigon (2016). Towards LTE physical layer virtualization on a COTS multicore platform with efficient scheduling14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), 4 pages. DOI : 10.1109/NEWCAS.2016.7604823 
25 G. Kazma, G.B. Hamad, O.A. Mohamed, Y. Savaria (2016). Investigating the efficiency and accuracy of a data type reduction technique for soft error analysisIEEE International Conference on Electronics, Circuits and Systems (ICECS 2016), p. 273-276. DOI : 10.1109/ICECS.2016.7841185 
26 R. Alizadeh, Y. Savaria (2016). Performance analysis of a reduced complexity SCMA decoder exploiting a low-complexity maximum-likelihood approximation23rd IEEE International Conference on Electronics Circuits and Systems (ICECS 2016), p. 253-256. DOI : 10.1109/icecs.2016.7841180 
27 M. Ammar, G.B. Hamad, O.A. Mohamed, Y. Savaria (2016). Efficient probabilistic fault tree analysis of safety critical systems via probabilistic model checkingForum on Specification and Design Languages (FDL 2016), 8 pages. DOI : 10.1109/fdl.2016.7880373 
28 G.B. Hamad, G. Kazma, O.A. Mohamed, Y. Savaria (2016). Comprehensive non-functional analysis of combinational circuits vulnerability to single event transientsForum on Specification and Design Languages (FDL 2016), 7 pages. DOI : 10.1109/fdl.2016.7880371 
29 P. Nsame, G. Bois, Y. Savaria (2015). Analysis and characterization of data energy tradeoffs: for VLSI architectural agility in C-RAN platformsIEEE International Symposium on Circuits and Systems (ISCAS 2015), p. 1466-1469. DOI : 10.1109/ISCAS.2015.7168921 
30 Z. Mirzadeh, J.F. Boland, Y. Savaria (2015). Modeling the faulty behaviour of digital designs using a feed forward neural network approachIEEE International Symposium on Circuits and Systems (ISCAS 2015), p. 1518-1521. DOI : 10.1109/ISCAS.2015.7168934 
31 K.A. Hoque, O.A. Mohamed, Y. Savaria (2015). Towards an accurate reliability, availability and maintainability analysis approach for satellite systems based on probabilistic model checkingDesign, Automation and Test in Europe Conference and Exhibition (DATE 2015), p. 1635-1640.
32 M. Fiorentino, O. Al-Terkawi, Y. Savaria, C. Thibeault (2015). Self-timed circuits FPGA implementation flow13th IEEE International New Circuits and Systems Conference (NEWCAS 2015), 4 pages. DOI : 10.1109/NEWCAS.2015.7182063 
33 R. Alizadeh, N. Bélanger, Y. Savaria, J.F. Frigon (2015). DPDK and MKL; enabling technologies for near deterministic cloud-based signal processing13th IEEE International New Circuits and Systems Conference (NEWCAS 2015), 4 pages. DOI : 10.1109/NEWCAS.2015.7182086 
34 H. Abdollahifakhr, N. Bélanger, Y. Savaria, F. Gagnon (2015). Power-efficient hardware architecture for computing Split-Radix FFTs on highly sparsed spectrum13th IEEE International New Circuits and Systems Conference (NEWCAS 2015), 4 pages. DOI : 10.1109/NEWCAS.2015.7182096 
35 G.B. Hamad, S.R. Hasan, O.A. Mohamed, Y. Savaria (2015). Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuitsMicroelectronics Reliability, 55(1), p. 238-250. DOI : 10.1016/j.microrel.2014.09.025 
36 M. Mohajertehrani, U. Shafique, Y. Savaria, M. Sawan (2015). Harvesting energy from data lines for avionics applications: power conversion chain architecture27th International Conference on Microelectronics (ICM 2015), p. 55-58. DOI : 10.1109/ICM.2015.7437986 
37 W. Hussain, Y. Blaquiere, Y. Savaria (2015). An interface for open-drain bidirectional communication in field programmable interconnection networksIEEE Transactions on Circuits and Systems I: Regular Papers, 62(10), p. 2465-2475. DOI : 10.1109/TCSI.2015.2476297 
38 H. Khanzadi, Y. Savaria, J.P. David (2015). Mapping applications on two-level configurable hardwareNASA/ESA Conference on Adaptive Hardware and Systems (AHS 2015), 8 pages. DOI : 10.1109/AHS.2015.7231167 
39 M. Khelifi, D. Massicotte, Y. Savaria (2015). Parallel independent FFT implementation on intel processors and Xeon phi for LTE and OFDM systems1st IEEE Nordic Circuits and Systems Conference (NORCAS 2015), 4 pages. DOI : 10.1109/NORCHIP.2015.7364402 
40 G.B. Hamad, O.A. Mohamed, Y. Savaria (2015). Efficient Multilevel Formal Analysis and Estimation of Design Vulnerability to Single Event Transients21st International On-Line Testing Symposium (IOLTS 2015), p. 1-6. DOI : 10.1109/IOLTS.2015.7229818 
41 G. Sion, Y. Blaquiere, Y. Savaria (2015). Defect Diagnosis Algorithms for a Field Programmable Interconnect Network Embedded in a Very Large Area Integrated Circuit21st International On-Line Testing Symposium (IOLTS 2015), p. 83-88. DOI : 10.1109/IOLTS.2015.7229837 
42 H. Zarrabi, A. Al-Khalili, Y. Savaria (2014). Vt-conscious repeater insertion in power-managed VLSIInternational Symposium on Integrated Circuits (ISIC 2014), p. 99-102. DOI : 10.1109/ISICIR.2014.7029470 
43 F.Z. Tazi, C. Thibeault, Y. Savaria, S. Pichette, Y. Audet (2014). On extra delays affecting I/O blocks of an SRAM-based FPGA due to ionizing radiationIEEE Transactions on Nuclear Science, 61(6), p. 3138-3145. DOI : 10.1109/TNS.2014.2369417 
44 M.A. Shaheen, Y. Savaria, A.A. Hamoui (2014). Design and modeling of high-resolution multibit log-domain modulatorsAnalog Integrated Circuits and Signal Processing, 79(3), p. 569-582. DOI : 10.1007/s10470-014-0285-1 
45 M.A. Shaheen, A.A. Hamoui, Y. Savaria (2014). A current-output DAC for low-power low-noise log-domain modulators12th IEEE International New Circuits and Systems Conference (NEWCAS 2014), p. 281-284. DOI : 10.1109/NEWCAS.2014.6934037 
46 P. Nsame, G. Bois, Y. Savaria (2014). A data-driven energy efficient and flexible compute fabric architecture: For adaptive computing applied to ULSI of FFT21st IEEE International Conference on Electronics, Circuits and Systems (ICECS 2014), p. 750-753. DOI : 10.1109/ICECS.2014.7050094 
47 M. Li, M. Lauer, G. Zhu, Y. Savaria (2014). Determinism enhancement of AFDX networks via frame insertion and sub-virtual link aggregationIEEE Transactions on Industrial Informatics, 10(3), p. 1684-1695. DOI : 10.1109/TII.2014.2315441 
48 N. Laflamme-Mayer, Y. Blaquiere, Y. Savaria, M. Sawan (2014). A configurable multi-rail power and I/O pad applied to wafer-scale systemsIEEE Transactions on Circuits and Systems I: Regular Papers, 61(11), p. 3135-3144. DOI : 10.1109/TCSI.2014.2334911 
49 G. Kowarzyk, N. Belanger, D. Haccoun, Y. Savaria (2014). Optimizing the parallel tree-search for finding shortest-span error-correcting CDO codesIEEE Transactions on Parallel and Distributed Systems, 25(11), p. 2992-3001. DOI : 10.1109/TPDS.2013.311 
50 T. Keklikian, J.M.P. Langlois, Y. Savaria (2014). A Memory Transaction Model for Sparse Matrix-Vector Multiplications on GPUs12th IEEE International New Circuits and Systems Conference (NEWCAS 2014). DOI : 10.1109/NEWCAS.2014.6934044 
51 K.A. Hoque, O.A. Mohamed, Y. Savaria, C. Thibeault (2014). Probabilistic model checking based DAL analysis to optimize a combined TMR-blind-scrubbing mitigation technique for FPGA-based aerospace applications12th ACM/IEEE International Conference on Methods and Models for System Design (MEMOCODE 2014), p. 175-184. DOI : 10.1109/MEMCOD.2014.6961856 
52 G.B. Hamad, O.A. Mohamed, Y. Savaria (2014). Probabilistic model checking of single event transient propagation at RTL level21st IEEE International Conference on Electronics, Circuits and Systems (ICECS 2014), p. 451-454. DOI : 10.1109/ICECS.2014.7050019 
53 Q.F. Gan, J.M.P. Langlois, Y. Savaria (2014). Efficient Uniform Quantization Likelihood Evaluation for Particle Filters in Embedded ImplementationsJournal of Signal Processing Systems for Signal Image and Video Technology, 75(3), p. 191-202. DOI : 10.1007/s11265-013-0798-3 
54 Q. Gan, J.M.P. Langlois, Y. Savaria (2014). A Parallel Systematic Resampling Algorithm for High-Speed Particle Filters in Embedded SystemsCircuits, Systems & Signal Processing, 33(11), p. 3591-3602. DOI : 10.1007/s00034-014-9820-7 
55 A. Fischer, R. Plamondon, Y. Savaria, K. Riesen, H. Bunke (2014). A Hausdorff heuristic for efficient computation of graph edit distanceJoint IAPR International Workshop on Structural, Syntactic, and Statistical Pattern Recognition (S+SSPR 2014), v. 8621 LNCS, p. 83-92. DOI : 10.1007/978-3-662-44415-3_9 
56 A. Fischer, R. Plamondon, C. O'Reilly, Y. Savaria (2014). Neuromuscular representation and synthetic generation of handwritten whiteboard notes14th International Conference on Frontiers in Handwriting Recognition (ICFHR 2014), p. 222-7. DOI : 10.1109/ICFHR.2014.45 
57 R. Farah, Q. Gan, J.M.P. Langlois, G.-A. Bilodeau, Y. Savaria (2014). A computationally efficient importance sampling tracking algorithmMachine Vision and Applications, 25(7), p. 1761-1777. DOI : 10.1007/s00138-014-0630-5 
58 R. Deca, O. Cherkaoui, Y. Savaria (2014). Constraint-based configuration complexity model for autonomic network configuration managementGlobal Information Infrastructure and Networking Symposium (GIIS 2014). DOI : 10.1109/GIIS.2014.6934272 
59 K.A. Hoque, O. Ait Mohamed, Y. Savaria, C. Thibeault (2013). Early analysis of soft error effects for aerospace applications using probabilistic model checking2nd International Workshop of Formal Techniques for Safety-Critical Systems (FTSCS 2013), v. 419 CCIS, p. 54-70. DOI : 10.1007/978-3-319-05416-2_5 
60 J. Tremblay, Y. Savaria, G. Zhu, C. Ghibeault, S. Bouanen (2013). A hardware prototype for integration, test and validation of avionic networks. 32nd IEEE/AIAA Digital Avionics Systems Conference (DASC 2013), p. 2D5-1 - 2D5-11.
61 A. Trabelsi, Y. Savaria (2013). A 2D Gaussian smoothing kernel mapped to heterogeneous platforms11th IEEE International New Circuits and Systems Conference (NEWCAS 2013). DOI : 10.1109/NEWCAS.2013.6573641 
62 C. Thibeault, Y. Hariri, S.R. Hasan, C. Hobeika, Y. Savaria, Y. Audet, F.Z. Tazi (2013). A library-based early soft error sensitivity analysis technique for SRAM-based FPGA design. Journal of Electronic Testing: Theory and Applications, 29(4), p. 457-471.
63 M.A. Tehrani, J.J. Laurin, Y. Savaria (2013). Angular superresolution algorithm for frequency scanning array antennasIEEE Radar Conference (RadarCon 2013). DOI : 10.1109/RADAR.2013.6586118 
64 T. Stimpfling, Y. Savaria, A. Beliveau, N. Belanger, O. Cherkaoui (2013). Optimal packet classification applicable tothe OpenFlow context. 1st ACM Workshop on High Performance and Programmable Networking (HPPN 2013), p. 9-14.
65 R. Robache, J.-F. Boland, C. Thibeault, Y. Savaria (2013). A methodology for system-level fault injection based on gate-level faulty behavior. 11th IEEE International New Circuits and Systems Conference (NEWCAS 2013).
66 J.-F. Pons, J.-J. Brault, Y. Savaria (2013). Modeling, Design and Implementation of a Low-Power Fpga Based Asynchronous Wake-up Receiver for Wireless Applications. Analog Integrated Circuits and Signal Processing, 77(2), p. 169-182.
67 A. Lakhssassi, R. Palenychka, M. Sayde, Y. Savaria, M. Zaremba, E. Kengne (2013). A spatiotemporal attention operator for monitoring thermo-mechanical stress in wafer-scale integrated circuits using an infrared camera. 8th International Symposium on Image and Signal Processing and Analysis (ISPA 2013), p. 165-70.
68 G. Kowarzyk, N. Belanger, D. Haccoun, Y. Savaria (2013). Efficient parallel search algorithm for determining optimal R=1/2 systematic convolutional self-doubly orthogonal codes. IEEE Transactions on Communications, 61(3), p. 865-876.
69 W. Hussain, Y. Savaria, Y. Blaquière (2013). An interface for the I2C protocol in the WaferBoard TM. IEEE International Symposium on Circuits and Systems (ISCAS 2013).
70 G.B. Hamad, S.R. Hasan, O.A. Mohamed, Y. Savaria (2013). Investigating the impact of propagation paths and re-convergent paths on the propagation induced pulse broadening14th European Conference on Radiation and Its Effects on Components and Systems (RADECS 2013), p. 1-4. DOI : 10.1109/RADECS.2013.6937387 
71 G.B. Hamad, S.R. Hasan, O.A. Mohamed, Y. Savaria (2013). Investigating the impact of input patterns, propagation paths, and re-convergent paths on the propagation induced pulse broadening. Radiation Effects on Components and Systems (RADECS 2013).
72 M. Guillemot, Y. Blaquiere, Y. Savaria (2013). Software Rendering Methods to Display Wafer Scale Integrated Circuit Dataset. 26th Annual IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2013), p. 819-822.
73 D.C. Gill, J.M.P. Langlois, Y. Savaria (2013). Accelarating a modified gaussian pyramid with a customized processor. Conference on Design and Architectures for Signal and Image Processing (DASIP 2013), p. 259-264.
74 Q. Gan, J.M.P. Langlois, Y. Savaria (2013). A reformulated systematic resampling algorithm for particle filters and its parallel implementation in an application-specific instruction-set processor. 56th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2013), p. 1415-1418.
75 Q. Gan, J.M.P. Langlois, Y. Savaria (2013). Parallel array histogram architecture for embedded implementationsElectronics Letters, 49(2), p. 99-101. DOI : 10.1049/el.2012.2701 
76 S. Bouanen, C. Thibeault, Y. Savaria, J.P. Tremblay (2013). Fault tolerant smart transducer interface for safety-critical avionics applications. 32nd IEEE/AIAA Digital Avionics Systems Conference (DASC 2013).
77 K. Baratli, A. Lakhssassi, Y. Blaquiere, Y. Savaria (2013). A netlist pruning tool for an electronic system prototyping platform. 11th IEEE International New Circuits and Systems Conference (NEWCAS 2013).
78 D. Trentin, Y. Savaria, G. Zhu, C. Thibeault (2012). An AFDX Switch Fabric Hardware Core for Avionic Network Prototyping and Characterization. SAE International Journal of Aerospace, 5(1), p. 181-188.
79 J.-P. Tremblay, Y. Savaria, G. Zhu, C. Thibeault, S. Bouanen (2012). A System Architecture for Smart Sensors Integration in Avionics Applications. SAE International Journal of Aerospace, 5(1), p. 189-195.
80 C. Thibeault, S. Pichette, Y. Audet, Y. Savaria, H. Rufenacht, E. Gloutnay, Y. Blaquiere, F. Moupfouma, N. Batani (2012). On Extra Combinational Delays in SRAM FPGAs Due to Transient Ionizing Radiations. IEEE Transactions on Nuclear Science, 59(6), p. 2959-65.
81 J.-F. Pons, J.-J. Brault, Y. Savaria (2012). State-holding free NULL Convention Logic55th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2012), p. 322-325. DOI : 10.1109/MWSCAS.2012.6292022 
82 J.-F. Pons, J.-J. Brault, Y. Savaria (2012). An FPGA compatible asynchronous wake-up receiver for Wireless Sensor Networks. 10th IEEE International New Circuits and Systems Conference (NEWCAS 2012), p. 373-376.
83 A. Nourivand, A.J. Al-Khalili, Y. Savaria (2012). Postsilicon Tuning of Standby Supply Voltage in Srams to Reduce Yield Losses Due to Parametric Data-Retention Failures. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(1), p. 29-41.
84 R. Nishi, G. Zhu, Y. Savaria (2012). Optimal scheduling policy for AFDX end-systems with virtual links of identical bandwidth allocation gap size. 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2012).
85 H.H. Nguyen, M. Guillemot, Y. Savaria, Y. Blaquiere (2012). A new approach for pin detection for an electronic system prototyping reconfigurable platform. 23rd IEEE International Symposium on Rapid System Prototyping (RSP 2012), p. 122-7.
86 M.M. Mbaye, N. Belanger, Y. Savaria, S. Pierre (2012). Loop Acceleration Exploration for Asip Architecture. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(4), p. 684-696.
87 H. Mahvash Mohammadi, Y. Savaria, J.M.P. Langlois (2012). Enhanced motion compensated deinterlacing algorithm. IET Image Processing, 6(8), p. 1041-8.
88 G. Kowarzyk, N. Belanger, D. Haccoun, Y. Savaria (2012). Efficient Search Algorithm for Determining Optimal R=1/2 Systematic Convolutional Self-Doubly Orthogonal Codes. IEEE Transactions on Communications, 60(1), p. 3-8.
89 S.S. Hashemi, M. Sawan, Y. Savaria (2012). A high-efficiency low-voltage CMOS rectifier for harvesting energy in implantable devices. IEEE Transactions on Biomedical Circuits and Systems, 6(4), p. 326-335.
90 R. Deca, O. Cherkaoui, Y. Savaria (2012). Rule-based network service provisioning. Journal of Networks, 7(10), p. 1493-1504.
91 G. Bany Hamad, O. Ait Mohamed, S. Rafay Hasan, Y. Savaria (2012). Identification of soft error glitch-propagation paths: Leveraging SAT solvers. IEEE International Symposium on Circuits and Systems (ISCAS 2012), p. 3258-3261.
92 P. Aubertin, J.M.P. Langlois, Y. Savaria (2012). Real-time computation of local neighborhood functions in application-specific instruction-set processors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(11), p. 2031-2043.
93 A. Anane, E.M. Aboulhamid, Y. Savaria (2012). System modeling and multicore simulation using transactions. International Conference on Embedded Computer Systems (SAMOS 2012), p. 41-50.
94 O. Al-Terkawi Hasib, W. Andre, Y. Blaquiere, Y. Savaria (2012). Propagating analog signals through a fully digital network on an electronic system prototyping platform. IEEE International Symposium on Circuits and Systems (ISCAS 2012), p. 1983-1986.
95 M. Allard, P. Grogan, Y. Savaria, J.-P. David (2012). Two-level configuration for FPGA: A new design methodology based on a computing fabric. IEEE International Symposium on Circuits and Systems (ISCAS 2012), p. 265-268.
96 Z. Al-Bayati, O. Ait Mohamed, Y. Savaria, M. Boukadoum (2012). Probabilistic model checking of clock domain crossing interfaces. 10th IEEE International New Circuits and Systems Conference (NEWCAS 2012), p. 193-196.
97 Z. Al-Bayati, O. Ait Mohamed, S.R. Hasan, Y. Savaria (2012). A novel hybrid FIFO asynchronous clock domain crossing interfacing method. 22nd Great Lakes Symposium on VLSI (GLSVLSI 2012), p. 271-274.
98 H. Zarrabi, A.J. Al-Khalili, Y. Savaria (2011). Activity management in battery-powered embedded systems: A case study of ZigBee&reg WSN. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), p. 727-731.
99 H. Zarrabi, A. Al-Khalili, Y. Savaria (2011). Repeater insertion in power-managed VLSI systems. 21st Great Lakes Symposium on VLSI (GLSVLSI 2011), p. 395-398.
100 O. Valorge, W. Andre, Y. Savaria, Y. Blaquieie (2011). Power supply analysis of a large area integrated circuit. 9th IEEE International New Circuits and Systems Conference (NEWCAS 2011), p. 398-401.
101 S. Vakili, D.C. Gil, J.M.P. Langlois, Y. Savaria, G. Bois (2011). Customized embedded processor design for global photographic tone mapping. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), p. 382-385.
102 M. Tawk, G. Zhu, Y. Savaria, X. Liu, J. Li, F. Hu (2011). A tight end-to-end delay bound and scheduling optimization of an avionics AFDX network. 30th Digital Avionics Systems Conference (DASC 2011), p. 7B31-7B310.
103 M. Tawk, G. Zhu, X. Liu, L. Jian, Y. Savaria, F. Hu (2011). Optimal scheduling and delay analysis for AFDX end-systems. SAE AeroTech Congress and Exhibition (AEROTECH 2011).
104 R. Singh, Y. Audet, Y. Gagnon, Y. Savaria, E. Boulais, M. Meunier (2011). A laser-trimmed rail-to-rail precision CMOS operational amplifier. IEEE Transactions on Circuits and Systems II: Express Briefs, 58(2), p. 75-79.
105 A. Nourivand, A.J. Al-Khalili, Y. Savaria (2011). Analysis of resistive open defects in drowsy SRAM cells. Journal of Electronic Testing: Theory and Applications, 27(2), p. 203-213.
106 H. Mahvash Mohammadi, Y. Savaria, J.M.P. Langlois (2011). Hybrid video deinterlacing algorithm exploiting reverse motion estimation. IET Image Processing, 5(7), p. 611-618.
107 G. Kowarzyk, N. Belanger, Y. Savaria (2011). A GPGPU-based software implementation of the PBDI deinterlacing algorithm. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), p. 780-783.
108 S.R. Hasan, N. Belanger, Y. Savaria, M.O. Ahmad (2011). All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs. Integration, the VLSI Journal, 44(1), p. 22-38.
109 D.C. Gil, R. Farah, J.M.P. Langlois, G.-A. Bilodeau, Y. Savaria (2011). Comparative analysis of contrast enhancement algorithms in surveillance imaging. IEEE International Symposium of Circuits and Systems (ISCAS 2011), p. 849-852.
110 R. Farah, Q. Gan, J.M.P. Langlois, G.-A. Bilodeau, Y. Savaria (2011). A tracking algorithm suitable for embedded systems implementation. 18th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2011), p. 256-259.
111 E. Boulais, J. Fantoni, A. Chateauneuf, Y. Savaria, M. Meunier (2011). Laser-induced resistance fine tuning of integrated polysilicon thin-film resistors. IEEE Transactions on Electron Devices, 58(2), p. 572-575.
112 O. Al-Terkawi Hasib, M. Sawan, Y. Savaria (2011). A low-power asynchronous step-down DCDC converter for implantable devices. IEEE Transactions on Biomedical Circuits and Systems, 5(3), p. 292-301.
113 H. Zarrabi, A.J. Al-Khalili, Y. Savaria (2010). An interconnect-aware Dynamic Voltage Scaling scheme for DSM VLSI. IEEE International Symposium on Circuits and Systems (ISCAS 2010), p. 41-44.
114 L.-F. Tanguay, Y. Savaria, M. Sawan (2010). A 640 W frequency synthesizer dedicated to implantable medical microsystems in 90-nm CMOS. 8th IEEE International NEWCAS Conference (NEWCAS 2010), p. 369-372.
115 D. Marche, Y. Savaria (2010). Modeling R-2R segmented-ladder DACs. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(1), p. 31-43.
116 O.A. Hasib, M. Sawan, Y. Savaria (2010). Fully integrated ultra-low-power asynchronously driven step-down DC-DC converter. IEEE International Symposium on Circuits and Systems (ISCAS 2010), p. 877-880.
117 S.R. Hasan, N. Belanger, Y. Savaria, M.O. Ahmad (2010). Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(10), p. 2696-707.
118 S.R. Hasan, N. Belanger, Y. Savaria, M.O. Ahmad (2010). Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(8), p. 2020-2031.
119 R. Chebli, M. Sawan, K. El-Sankary, Y. Savaria (2010). High-voltage DMOS integrated circuits using floating-gate protection technique. Analog Integrated Circuits and Signal Processing, 62(2), p. 223-235.
120 O. Berriah, M. Bougataya, A. Lakhssassi, Y. Blaquiere, Y. Savaria (2010). Thermal analysis of a miniature electronic power device matched to a silicon wafer. 8th IEEE International NEWCAS Conference (NEWCAS 2010), p. 129-132.
121 H. Zarreabi, A.J. Al-Khalili, Y. Savaria (2009). Estimation of energy performance in computing platforms. 16th IEEE International Conference on Electronics, Circuits and Systems, p. 783-786.
122 H. Zarrabi, A.J. Al-Khalili, Y. Savaria (2009). An interconnect-aware delay model for dynamic voltage scaling in nm technologies. 19th ACM Great Lakes Symposium on VLSI, p. 45-49.
123 L.-F. Tanguay, M. Sawan, Y. Savaria (2009). A very-high output impedance charge pump for low-voltage low-power PLLs. Microelectronics Journal, 40(6), p. 1026-1031.
124 A. Naderi, M. Sawan, Y. Savaria (2009). Undersampling delta-sigma modulators : theory, design and implementation. Lambert Academic Publishers. .
125 A. Naderi, M. Sawan, Y. Savaria (2009). A low-power 2 GHz data conversion using delta modulation for portable application. Integration, the VLSI Journal, 42(1), p. 68-76.
126 D. Marche, Y. Savaria, Y. Gagnon (2009). An improved switch compensation technique for inverted R-2R Ladder DACs. IEEE Transactions on Circuits and Systems I: Regular Papers, 56(6), p. 1115-1124.
127 P. Mahoney, Y. Savaria, G. Bois, P. Plante (2009). Performance characterization for the implementation of content addressable memories based on parallel hashing memories. Transactions on High-Performance Embedded Architectures and Compilers. II. Berlin, Germany: Springer Verlag. p. 307-325.
128 E. Lepercq, O. Valorege, Y. Basile-Bellavance, N. Laflamme-Mayer, Y. Blaquière, Y. Savaria (2009). An interconnection network for a novel reconfigurable circuit board. 2nd Microsystems and Nanoelectronics Research Conference, p. 128-131.
129 E. Lepercq, Y. Blaquiere, R. Norman, Y. Savaria (2009). Workflow for an electronic configurable prototyping system. IEEE International Symposium on Circuits and Systems (ISCAS 2009), p. 2005-2008.
130 A. Lacourse, M. Ducharme, H. St-Jean, Y. Gagnon, Y. Savaria, M. Meunier (2009). Tunable semiconductor component provided with a current barrier. (No de brevet - US 7564078).
131 S. Hashemi, M. Sawan, Y. Savaria (2009). A low-area power-efficient CMOS active rectifier for wirelessly powered medical devices. 16th IEEE International Conference on Electronics, Circuits and Systems, p. 635-638.
132 S. Hashemi, M. Sawan, Y. Savaria (2009). Fully-integrated low-voltage high-efficiency CMOS rectifier for wirelessly powered devices. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009).
133 S. Hashemi, M. Sawan, Y. Savaria (2009). A novel low-drop CMOS active rectifier for RF-powered devices: Experimental results. Microelectronics Journal, 40(11), p. 1547-1554.
134 S.R. Hasan, B. Pontikakis, Y. Savaria (2009). An all-digital skew-adaptive clock scheduling algorithm for heterogeneous multiprocessor systems on chips (MPSoCs). IEEE International Symposium on Circuits and Systems (ISCAS 2009), p. 2501-2504.
135 N. Beucher, N. Belanger, Y. Savaria, G. Bois (2009). High acceleration for video processing applications using specialized instruction set based on parallelism and data reuse. Journal of Signal Processing Systems, 56(2-3), p. 155-165.
136 Y. Basile-Bellavance, Y. Blaquiere, Y. Savaria (2009). Faults diagnosis methodology for the WaferNet interconnection network. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009).
137 D. Bafumba-Lokilo, Y. Savaria, J.-P. David (2009). Generic array-based MPSoC architecture. 2nd Microsystems and Nanoelectronics Research Conference, p. 128-131.
138 D. Ayachi, Y. Savaria, C. Thibeault (2009). A configurable platform for MPSoCs based on application specific instruction set processors. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009).
139 P. Aubertin, H.M. Mohammadi, Y. Savaria, J.M.P. Langlois (2009). High performance ASIP implementation of PBDI: a new intra-field deinterlacing method. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009).
140 O. Valorge, A.T. Nguyen, Y. Blaquière, R. Norman, Y. Savaria (2008). Digital signal propagation on a wafer-scale smart active programmable interconnect. 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008), p. 1059-1062.
141 J.-P. Tremblay, Y. Savaria, C. Thibeault, M. Mbaye (2008). Improving resource utilization in an multiple asynchronous ALU DSP architecture. 1st Microsystems and Nanoelectronics Research Conference, p. 25-28.
142 L.F. Tanguay, M. Sawan, Y. Savaria (2008). A very-high output impedance current mirror for very-low voltage biomedical analog circuits. IEEE Asia-Pacific Conference on Circuits and Systems, p. 642-645.
143 M.E. Salomon, B. Izouggaghen, A. Khouas, Y. Savaria (2008). Spur Model for a Fixed-Frequency Signal Subject to Periodic Jitter. IEEE Transactions on Instrumentation and Measurement, 57(10), p. 2320-2328.
144 N. Sahraii, Y. Savaria, C. Thibeault, F. Gagnon (2008). Scheduling of turbo decoding on a multiprocessor platform to manage its processing effort variability. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), p. 73-76.
145 B. Pontikakis, H.T. Bui, F.-R. Boyer, Y. Savaria (2008). A novel phase-locked loop (PLL) architecture without an analog loop filter for better integration in ultra-deep submicron SoCs. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), p. 363-366.
146 A. Nourivand, A.J. Al-Khalili, Y. Savaria (2008). Aggressive leakage reduction of SRAMs using error checking and correcting (ECC) techniques. 51st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2008), p. 426-429.
147 R. Norman, O. Valorge, Y. Blaquiere, E. Lepercq, Y. Basile-Bellavance, Y. El-Alaoui, R. Prytula, Y. Savaria (2008). An active reconfigurable circuit board. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), p. 351-354.
148 R. Norman, E. Lepercq, Y. Blaquiere, O. Valorge, Y. Basile-Bellavance, R. Prytula, Y. Savaria (2008). An interconnection network for a novel reconfigurable circuit board. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), p. 129-132.
149 G.-A.B. Ngoyi, J.M.P. Langlois, Y. Savaria (2008). Iterative design method for video processors based on an architecture design language and its application to ELA deinterlacing. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), p. 37-40.
150 A. Naderi, M. Sawan, Y. Savaria (2008). On the design of undersampling continuous-time bandpass delta - Sigma modulators for gigahertz frequency A/D conversion. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(11), p. 3488-3499.
151 M. Mbaye, N. Belanger, Y. Savaria, S. Pierre (2008). Loop-oriented metrics for exploring an application-specific architecture design-space. International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2008), p. 257-262.
152 D. Marche, Y. Savaria, Y. Gagnon (2008). Laser Fine-Tuneable Deep-Submicrometer Cmos 14-Bit Dac. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(8), p. 2157-2165.
153 Z. Lu, J. El-Fouladi, S. Martel, Y. Savaria (2008). A hybrid bacteria and microparticle detection platform on a CMOS chip: design, simulation and testing considerations. 14th IEEE International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW 2008).
154 G. Kowarzyk, Y. Savaria, D. Haccoun (2008). Searching for short-span convolutional doubly self-orthogonal codes: a parallel implicitly-exhaustive-search algorithm. Canadian Conference on Electrical and Computer Engineering (CCECE 2008), p. 001659-001662.
155 S.R. Hasan, N. Bélanger, Y. Savaria (2008). All digital skew tolerant synchronous intrfacing methods for high-performance point-to-point communication in DSM SoCs(Rapport 2008-10). 53 pages.
156 S.R. Hasan, N. Belanger, Y. Savaria (2008). All-digital skew-tolerant interfacing method for systems with rational frequency ratios among multiple clock domains: leveraging a priori timing information. 1st Microsystems and Nanoelectronics Research Conference, p. 129-132.
157 H.T. Bui, Y. Savaria (2008). Design of a High-Speed Differential Frequency-to-Voltage Converter and Its Application in a 5-Ghz Frequency-Locked Loop. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(3), p. 766-774.
158 E. Boulais, V. Binet, J.Y. Degorce, G. Wild, Y. Savaria, M. Meunier (2008). Thermodynamics and Transport Model of Charge Injection in Silicon Irradiated by a Pulsed Focused Laser. IEEE Transactions on Electron Devices, 55(10), p. 2728-2735.
159 M. Bougataya, A. Lakhsasi, R. Norman, R. Prytula, Y. Blaquière, Y. Savaria (2008). Steady state thermal analysis of a reconfigurable wafer-scale circuit board. IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2008), p. 411-415.
160 Y. Basile-Bellavance, E. Lepercq, Y. Blaquiere, Y. Savaria (2008). Hardware/software system co-verification of an active reconfigurable board with SystemC-VHDL. 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008), p. 1159-1162.
161 D. Bafumba-Lokilo, Y. Savaria, J.-P. David (2008). Generic crossbar network on chip for FPGA MPSoCs. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008), p. 269-272.
162 A. Anane, E.M. Aboulhamid, J. Vachon, Y. Savaria (2008). Modeling and simulation of complex heterogeneous systems. IEEE International Symposium on Circuits and Systems (ISCAS 2008), p. 2873-2876.
163 O. Valorge, D. Marche, A. Lacourse, M. Sawan, Y. Savaria (2007). Signal Integrity Analysis of a High Precision D/A Converter. 14th IEEE International Conference on Electronics, Circuits and Systems, p. 1224-1227.
164 A. Trabelsi, F.R. Boyer, Y. Savaria (2007). Speech enhancement based noise PSD estimator to remove cosine shaped residual noise. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007), p. 393-396.
165 A. Trabelisi, F.R. Boyer, Y. Savaria, M. Boukadoum (2007). Improving LPC Analysis of Speech in Additive Noise. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), p. 93-96.
166 A. Trabelisi, F.R. Boyer, Y. Savaria, M. Boukadoum (2007). Iterative Noise-Compensated Method to Improve LPC Based Speech Analysis. 14h IEEE International Conference on Electronics, Circuits & Systems, p. 1364-1367.
167 R. Singh, Y. Audet, Y. Gagnon, Y. Savaria (2007). Integrated circuit trimming technique for offset reduction in a precision CMOS amplifier. IEEE International Symposium on Circuits and Systems (ISCAS 2007), p. 709-712.
168 J.-F. Saheb, J.-F. Richard, M. Sawan, R. Meingan, Y. Savaria (2007). System integration of high voltage electrostatic MEMS actuators. Analog Integrated Circuits and Signal Processing, 53(1), p. 27-34.
169 B. Pontikakis, H.T. Bui, F.-R. Boyer, Y. Savaria (2007). A low-complexity high-speed clock generator for dynamic frequency scaling of FPGA and standard-cell based designs. IEEE International Symposium on Circuits and Systems (ISCAS 2007), p. 633-636.
170 B. Pontikakis, F.-R. Boyer, Y. Savaria, H.T. Bui (2007). Precise free-running period synthesizer (FRPS) with process and temperature compensation. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007), p. 1118-1121.
171 A. Naderi, M. Sawan, Y. Savaria (2007). A 1.8GHz CMOS continuous-time band-pass delta-sigma modulator for RF receivers. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007), p. 1078-1081.
172 H.M. Mohammadi, J.M.P. Langlois, Y. Savaria (2007). A Five-Field Motion Compensated Deinterlacing Method Based on Vertical Motion. IEEE Transactions on Consumer Electronics, 53(3), p. 1117-1124.
173 M. Meunier, Y. Gagnon, A. Lacourse, M. Ducharme, S. Rioux, Y. Savaria (2007). Precision resistor laser trimming for analog microelectronics. Photonic Applications Systems Technologies Conference.
174 M.M. Mbaye, N. Belanger, Y. Savaria, S. Pierre (2007). A Novel Application-Specific Instruction-Set Processor Design Approach for Video Processing Acceleration. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, 47(3), p. 297-315.
175 Z. Lu, J. El-Fouladi, Y. Savaria, S. Martel (2007). A hybrid bacteria and microparticle detection platform on a CMOS chip. 11th International Conference on Miniaturized Systems for Chemistry and Life Science.
176 S. Hashemi, M. Sawan, Y. Savaria (2007). A novel fully-integrated low-drop voltage cmos rectifier for wirelessly powered devices. IEEE International Conference on Microelectronics, p. 333-336.
177 N. Gorse, P. Belanger, A. Chureau, E.M. Aboulhamid, Y. Savaria (2007). A High-Level Requirements Engineering Methodology for Electronic System-Level Design. Computers & Electrical Engineering, 33(4), p. 249-268.
178 J. El Fouladi, Z. Lu, Y. Savaria, S. Martel (2007). An integrated biosensor for the detection of bio-entities using magnetotactic bacteria and CMOS technology.. 29th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC 2007), v. 2007, p. 119-122.
179 R. Deca, O. Cherkaoui, Y. Savaria, D. Slone (2007). Constraint-Based Model Service for Network Provisioning. Annales des télécommunications, 62(7-8), p. 847-870.
180 R. Chebli, M. Sawan, Y. Savaria, K. El-Sankary (2007). High-voltage DMOS integrated circuits with floating gate protection technique. IEEE International Symposium on Circuits and Systems (ISCAS 2007), p. 3343-3346.
181 V. Binet, Y. Savaria, M. Meunier, Y. Gagnon (2007). Modeling the substrate noise injected by a DC-DC converter. IEEE International Symposium on Circuits and Systems (ISCAS 2007), p. 309-312.
182 A. Abderrahman, Y. Savaria, A. Khouas, M. Sawan (2007). Accurate testability analysis based-on multi-frequency test generation and a new testability metric. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), p. 1356-1359.
183 A. Abderrahman, Y. Savaria, A. Khouas, M. Sawan (2007). New Analog Test Metrics Based on Probabilistic and Deterministic Combination Approaches. 14th IEEE International Conference on Electronics, Circuits and Systems, p. 82-85.
184 A. Trabelsi, F.-R. Boyer, Y. Savaria (2006). On the application of minimum noise tracking to cancel cosine shaped residual noise(Rapport 2006-09). 23 pages.
185 B. Pontikakis, F.-R. Boyer, Y. Savaria (2006). A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs. IEEE International Symposium on Circuits and Systems (ISCAS 2006), p. 1259-1262.
186 B. Nicolescu, N. Ignat, Y. Savaria, G. Nicolescu (2006). Analysis of real-time systems sensitivity to transient faults using MicroC kernel. IEEE Transactions on Nuclear Science, 53(4), p. 1902-1909.
187 A. Naderi, M. Sawan, Y. Savaria (2006). Design of an active-RC bandpass filter for a subsampling RF delta modulator. Canadian Conference on Electrical and Computer Engineering (CCECE 2006), p. 967-970.
188 A. Naderi, M. Sawan, Y. Savaria (2006). A novel 2-GHz band-pass delta modulator dedicated to wireless receivers. IEEE International Symposium on Circuits and Systems (ISCAS 2006).
189 H.M. Mohammadi, J.M.P. Langlois, Y. Savaria (2006). A threshold-based deinterlacing algorithm using motion compensation and directional interpolation. 13th IEEE International Conference on Electronics, Circuits and Systems, p. 459-462.
190 M. Mbaye, D. Lebel, N. Belanger, Y. Savaria, S. Pierre (2006). Design exploration with an application-specific instruction-set processor for ELA deinterlacing. IEEE International Symposium on Circuits and Systems (ISCAS 2006).
191 H. Mahvash Mohammadi, J.M.P. Langlois, Y. Savaria (2006). A threshold-based de-interlacing algorithm using motion compension and directional interpolation. IEEE International Conference on Electronics, Circuits and Systems (ICECS 2006).
192 M., H. Mahvash, Y. Savaria, J.M.P. Langlois (2006). Real-time ELA de-interlacing with the Xtensa reconfigurable processor. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006), p. 25-28.
193 N. Ignat, B. Nicolescu, Y. Savaria, G. Nicolescu (2006). Soft-Error Classification and Impact Analysis on Real-Time Operating Systems. Design, Automation and Test in Europe Conference and Exhibition (DATE 2006), p. 180-185.
194 Z. Huang, Y. Savaria, M. Sawan, R. Meinga (2006). High-voltage operational amplifier based on dual floating-gate transistors. IEEE International Symposium on Circuits and Systems (ISCAS 2006).
195 S. Hashemi, M. Sawan, Y. Savaria (2006). A power planning model for implantable stimulators. IEEE International Symposium on Circuits and Systems (ISCAS 2006).
196 J. El fouladi, W. André, Y. Savaria, S. Martel (2006). System design of an integrated measurement electronic subsystem for bacteria detection using and electrode array and MC-1 magnetotactic bacteria. International Workshop on Computer Architecture for Machine Perception and Sensing (CAMP 2006), p. 38-41.
197 M. Dubois, Y. Savaria, D. Haccoun, N. Belanger (2006). Low-power configurable and generic shift register hardware realisations for convolutional encoders and decoders. IEE Proceedings. Circuits, Devices and Systems, 153(3), p. 207-213.
198 F. Deslauriers, M. Langevin, G. Bois, Y. Savaria, P. Paulin (2006). RoC: a scalable network on chip based on the token ring concept. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006).
199 A. Chureau, Y. Savaria, J.-F. Boland, Z. Zilic, C. Thibeault, F. Gagnon (2006). Building heterogeneous functional prototypes using articulated interfaces. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006).
200 A. Castonguay, Y. Savaria (2006). Architecture of a hypertransport tunnel. IEEE International Symposium on Circuits and Systems (ISCAS 2006).
201 M.-A. Cantin, Y. Savaria, D. Prodanos, P. Lavoie (2006). A metric for automatic word-length determination of hardware datapaths. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(10), p. 2228-31.
202 H.T. Bui, Y. Savaria (2006). High speed differential pulse-width control loop based on frequency-to-voltage converters. 16th ACM Great Lakes Symposium on VLSI (GLSVLSI 2006).
203 F.R. Boyer, H.G. Epassa, Y. Savaria (2006). Embedded power-aware cycle by cycle variable speed processor. IEE Proceedings. Computers and Digital Techniques, 153(4), p. 283-290.
204 N. Belanger, Y. Savaria (2006). On the design of a double precision logarithmic number system arithmetic unit. 4th IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2006).
205 G. Wild, Y. Savaria, M. Meunier (2005). Characterization of Laser-Induced Photoexcitation Effect on a Surrounding CMOS Ring Oscillator. IEEE International Symposium on Circuits and Systems (ISCAS 2005), v. 4, p. 3696-3699.
206 M. Sawan, A. Djemouai, K. El-Sankary, H. Dang, A. Naderi, Y. Savaria, F. Gagnon (2005). High speed ADCs dedicated for wideband wireless receivers. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), p. 283-286.
207 M.E. Salomon, A. Khouas, Y. Savaria (2005). A Complete Spurs Distribution Model for Direct Digital Period Synthesizers. IEEE International Symposium on Circuits and Systems (ISCAS 2005), v. 5, p. 4859-4862.
208 J.F. Saheb, J.-F. Richard, R. Meingan, M. Sawan, Y. Savaria (2005). System integration of high voltage electrostatic MEMS Actuators. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), p. 155-158.
209 S. Rioux, A. Lacourse, M. Ducharme, Y. Gagnon, Y. Savaria, M. Meunier (2005). Design methods for CMOS low-current finely tunable voltage references covering a wide output range. IEEE International Symposium on Circuits and Systems (ISCAS 2005), p. 4257-4260.
210 G. Provost, M.A. Cantin, M. Sawan, C. C., Y. Savaria, D. Haccoun (2005). Fast parameters optimization of an iterative decoder using a configurable hardware accelerator. IEEE International Symposium on Circuits and Systems (ISCAS 2005), v. 4, p. 4159-4162.
211 B. Pontikakis, F.R. Boyer, Y. Savaria (2005). Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period. 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005), p. 454-458.
212 B. Nicolescu, N. Ignat, Y. Savaria, G. Nicolescu (2005). Sensitivity of real-time operating systems to transient faults : A cause study for microC kernel. 8th European Conference on Radiation and its Effects on Components and Systems (RADECS 2005).
213 B. Nicolescu, N. Gorse, Y. Savaria, E.M. Aboulhamid, R. Velazco (2005). On the Use of Model Checking for the Verification of a Dynamic Signature Monitoring Approach. IEEE Transactions on Nuclear Science, 52(5), p. 1555-1561.
214 A.H. Naderi, M. Sawan, Y. Savaria (2005). A 1-mW 2-GHz Q-enhanced LC bandpass filter for low-power RF applications. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), p. 365-368.
215 D. Morin, Y. Savaria, M. Sawan (2005). A 200 MSPS 10-bit pipelined ADC using digital calibration. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), p. 67-70.
216 M. Mbaye, N. Bélanger, Y. Savaria, S. Pierre (2005). Application Specific Instruction-Set Processor Generation for Video Processing Based on Loop Optimization. IEEE International Symposium on Circuits and Systems (ISCAS 2005), v. 4, p. 3515-3518.
217 D. Marche, Y. Savaria, Y. Gagnon (2005). A New Switch Compensation Technique for Inverted R-2r Ladder Dacs. IEEE International Symposium on Circuits and Systems (ISCAS 2005), v. 1, p. 196-199.
218 P. Mahoney, Y. Savaria, G. Bois, P. Plante (2005). Parallel hashing memories : an alternative to content addressable memories. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), p. 223-226.
219 W. Ling, Y. Savaria (2005). Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations. 6th International Symposium on Quality Electronic Design, p. 688-693.
220 A. Landry, Y. Savaria, M. Nekili (2005). Circuits techniques for a 2 GHz AMBA AHB Bus. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), p. 311-314.
221 A. Landry, M. Nekili, Y. Savaria (2005). A novel 2 GHz Mulit-layer AMBA high-Speed bus interconnect matrix for SoC platforms. IEEE International Symposium on Circuits and Systems (ISCAS 2005), p. 3343-3346.
222 H. Khali, Y. Savaria, J.-L. Houle (2005). A system level implementation strategy and partitioning algorithm for applications based on lookup tables. International Journal of Computer and Electrical Engineering, 31(7), p. 485-502.
223 S. Hashemi, M. Sawan, Y. Savaria (2005). Modeling power budget requirements of implantable electronic devices. IEEE International Conference on Electronics, Circuits and Systems (ICECS 2005).
224 R. Grou-Szabo, H. Ghattas, Y. Savaria, G. Nicolescu (2005). Component-Based Methodology for Hardware Design of a Dataflow Processing Network. 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005), p. 289-294.
225 H.G. Epassa, F.R. Boyer, Y. Savaria (2005). Implementation of a Cycle by Cycle Variable Speed Processor. IEEE International Symposium on Circuits and Systems (ISCAS 2005), v. 4, p. 3335-3338.
226 M. Dubois, Y. Savaria, D. Haccoun, N. Bélanger (2005). On low power configurable and generic shift register hardware realizations for convolutional encoders and decoders. IEE Proceedings. Circuits, Devices and Systems
227 M. Dubois, Y. Savaria, G. Bois (2005). A Generic Ahb Bus for Implementing High-Speed Locally Synchronous Islands. IEEE SoutheastCon 2004, p. 11-16.
228 R. Deca, O. Mahrez, O. Cherkaoui, Y. Savaria, D. Slone (2005). Contributions to automated testing of network service interactions. 5e Colloque International sur les nouvelles technologies de la répartition (NOTERE 2005), p. 175-180.
229 H. Dang, M. Sawan, Y. Savaria (2005). A Novel Approach for Implementing Ultra-High Speed Flash Adc Using Mcml Circuits. IEEE International Symposium on Circuits and Systems (ISCAS 2005), v. 6, p. 6158-6161.
230 A. Chureau, Y. Savaria, E.M. Aboulhamid (2005). The Role of Model-Level Transactors and Uml in Functional Prototyping of Systems-on-Chip: a Software-Radio Application. Design, Automation and Test in Europe Conference and Exhibition (DATE 2005), p. 698-703.
231 R. Chebli, M. Sawan, Y. Savaria (2005). A programmable posititve and negative high-voltage DC-DC converter dedicated for ultrasonic applications. 48th Midwest Symposium on Circuits and Systems (MWSCAS 2005), p. 679-682.
232 R. Chebli, M. Sawan, Y. Savaria (2005). Gate oxide protection in HV CMOS/DMOS integrated circuits: Design and experimental results. IEEE International Conference on Electronics, Circuits and Systems (ICECS 2005).
233 N. Chabini, E.M. Aboulhamid, I. Chabini, Y. Savaria (2005). Scheduling and Optimal Register Placement for Synchronous Circuits Derived Using Software Pipelining Techniques. ACM Transactions on Design Automation of Electronic Systems, 10(2), p. 187-204.
234 S. Catudal, M.A. Cantin, Y. Savaria (2005). Parameters Estimation Applied to Automatic Video Processing Algorithms Validation. IEEE International Symposium on Circuits and Systems (ISCAS 2005), v. 4, p. 3439-3442.
235 A. Castonguay, Y. Savaria (2005). A Hypertransport Chip-to-Chip Interconnect Tunnel Developed Using Systemc. 16th International Workshop on Rapid System Prototyping, p. 264-266.
236 H.T. Bui, Y. Savaria (2005). A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in Socs. 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005), p. 557-562.
237 H.T. Bui, Y. Savaria (2005). Design and analysis of XOR gates for high-speed and low-jitter applications. 9th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI 2005), p. 60-65.
238 H.T. Bui, Y. Savaria (2005). High-speed differential frequency-to-voltage converter. 3rd IEEE International Northeast Workshop on Circuits and Systems (NEWCAS 2005), p. 373-376.
239 H. Zhengrong, Y. Savaria, M. Sawan (2004). A dynamically controlled and refreshed low-power level-up shifter. 47th Midwest Symposium on Circuits and Systems (MWSCAS 2004), v. 1, p. 97-100.
240 B. Tohio, S. Pierre, Y. Savaria, m.M.M. Mbaye (2004). Protocol convertibility in network processing environments. 6th WSEAS International Conference on Telecommunications and Informatics (TELE-INFO 2004), v. 3, p. 1.
241 B. Tohio, S. Pierre, Y. Savaria, M.M. Mbaye (2004). Algorithm and criteria to assess protocol convertibility in network processing environments. WSEAS International Conference on Telecommunications and Informatics (TELE-INFO 2004).
242 B. Tanguay, Y. Savaria, M. Sawan (2004). Accelerating equalization algorithms using the Xtensa configurable processor. 16th International Conference on Microelectronics (ICM 2004), p. 434-437.
243 M. Robert, Y. Savaria, C. Wang (2004). Analysis of metrics used to compare analog-to-digital converters. 2nd Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), p. 301-304.
244 J.-F. Richard, Y. Savaria (2004). High voltage charge pump using standard CMOS technology. 2nd Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), p. 317-320.
245 S. Regimbal, Y. Savaria, G. Bois (2004). Verification strategy determination using dependence analysis of transaction-level models. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, p. 87-92.
246 K. Peterson, Y. Savaria (2004). Assertion-based on-line verification and debug environment for complex hardware systems. IEEE International Symposium on Circuits and Systems (ISCAS 2004), v. 2, p. 685-688.
247 P. Nsame, Y. Savaria (2004). A customizable embedded SoC platform architecture. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, p. 299-304.
248 P. Nsame, Y. Savaria (2004). Multi-processor SoC integration: a case study on BlueGene. IEEE International SOC Conference (SOCC 2004), p. 201-204.
249 B. Nicolescu, Y. Savaria, R. Velazco (2004). Performance evaluation and failure rate prediction for the soft implemented error detection technique. 10th IEEE International On-Line Testing Symposium, p. 233-238.
250 B. Nicolescu, Y. Savaria, R. Velazco (2004). Software detection mechanisms providing full coverage against single bit-flip faults. IEEE Transactions on Nuclear Science, 51(6), p. 3510-3518.
251 B. Nicolescu, N. Gorse, Y. Savaria, E.M. Aboulhamid, R. Velazco (2004). Validating a dynamic signature monitoring approach using the LTL mocel checking technique. Workshop on Radiation Effects on Components and Systems (RADECS 2004), p. 93-96.
252 D. Morin, F. Normandin, M.E. Grandmaison, H. Dang, Y. Savaria, M. Sawan (2004). An intellectual property module for auto-calibration of time-interleaved pipelined analog-to-digital converters. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, p. 111-114.
253 W. Ling, Y. Savaria (2004). Variable-precision multiplier for equalizer with adaptive modulation. 47th Midwest Symposium on Circuits and Systems (MWSCAS 2004), v. 1, p. 553-556.
254 M. Layachi, Y. Savaria, A. Rochefort (2004). The Effect of Pi-Coupling on the Electronic Properties of 1,4-Dithiol Benzene Stacking. International Conference on Mems, Nano and Smart Systems (ICMENS 2004), p. 588-592.
255 A. Landry, Y. Savaria, M. Nekili (2004). A beyond-1 GHz high-speed bus for SoC DSP platforms. 16th International Conference on Microelectronics (ICM 2004), p. 46-49.
256 L.-P. Lafrance, Y. Savaria (2004). A framework for implementing reusable digital signal processing modules. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, p. 51-4.
257 Z.-F. Jin, M. Yang, Y. Savaria, K. Wu (2004). Analysis of gate modulation in nanoscale field effect transistors using an equivalent substrate integrated waveguide (SIW) model10th International Symposium on Antenna Technology and Applied Electromagnetics and URSI Conference (ANTEM/URSI 2004), p. 63-65. DOI : 10.1109/antem.2004.7860633 
258 Y.T. Jiang, Y.K. Wang, X.Y. Song, Y. Savaria (2004). Computation of Signal Output Probability for Boolean Functions Represented by Obdd. Computers & Mathematics With Applications, 47(12), p. 1865-1874.
259 B. Izouggaghen, A. Khouas, Y. Savaria (2004). Spurs modeling in direct digital period synthesizers related to phase accumulator truncation. IEEE International Symposium on Circuits and Systems (ISCAS 2004), v. 3, p. 389-392.
260 Z. Huang, Y. Savaria, M. Sawan (2004). Robust design of a dynamically controlled low-power level-up shifter operating up to 300V. 2nd Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), p. 321-324.
261 S. Hashemi, M. Sawan, Y. Savaria (2004). Characterization of Stress Induced Defects in Deep Sub-Micron MOSFETS. 2nd Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), p. 329-332.
262 S.R. Hasan, A. Landry, Y. Savaria, M. Nekili (2004). Design constraints of hypertransport-compatible networks-on-chip. 2nd Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), p. 269-272.
263 E. Granger, S. Catudal, R. Grou, M.M. Mbaye, Y. Savaria (2004). On current strategies for hardware acceleration of digital image restoration filters. 4th WSEAS International Conference on Signal, Speech and Image Processing (ICOSSIP 2004).
264 N. Gorse, M. Metzger, J. Lapalme, E.M. Aboulhamid, y. Savaria, G. Nicolescu (2004). Enhancing ESys.Net with a semi-formal verification layer. 16th International Conference on Microelectronics (ICM 2004), p. 388-391.
265 N. Gorse, P. Bélanger, E.M. Aboulhamid, Y. Savaria (2004). Mixing linguistic and formal techniques for high-level requirements engineering. 16th International Conference on Microelectronics (ICM 2004), p. 339-342.
266 N. Gorse, E.M. Aboulhamid, Y. Savaria (2004). Consistency validation of high-level requirements. 4th International Workshop on System on Chip for Real Time Applications (IWSOC 2004), p. 93-98.
267 O. Duval, Y. Savaria (2004). An on-chip delay measurements module for nanostructures characterization. IEEE International Symposium on Circuits and Systems (ISCAS 2004), v. 3, p. 721-724.
268 O. Duval, L.P. Lafrance, Y. Savaria, R. Desjardins (2004). An Integrated Test Platform for Nanostructure Electrical Characterization. International Conference on Mems, Nano and Smart Systems (ICMENS 2004), p. 237-242.
269 M. Dubois, Y. Savaria, D. Haccoun (2004). On low power shift register hardware realizations for convolutional encoders and decoders. 2nd Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), p. 213-216.
270 M. Dubois, G. Bois, Y. Savaria (2004). Double profiling methodology for video processing platform. WSEAS Transactions on Computers, 3(6), p. 1802-1807.
271 A. Chureau, Y. Savaria, E.M. Aboulhamid (2004). Interface-based design of systems-on-chip using UML-RT. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, p. 39-44.
272 S. Catudal, M.-A. Cantin, Y. Savaria (2004). Performance driven validation applied to video processing. WSEAS Transactions on Electronics, 1(3), p. 568-575.
273 M.A. Cantin, Y. Savaria, R. Velazco (2004). An automatic word length determination method. WSEAS Transactions on Information Science & Applications, 1(5), p. 1440-1448.
274 M.A. Cantin, S. Regimbal, S. Catudal, Y. Savaria (2004). A Unified Environment to Assess Image Quality in Video Processing. Journal of Circuits, Systems and Computers, 13(6), p. 1289-1306.
275 D.E. Calbaza, I. Cordos, N. Seth-Smith, Y. Savaria (2004). An Adpll Circuit Using a Ddps for Genlock Applications. IEEE International Symposium on Circuits and Systems (ISCAS 2004), v. 4, p. 569-572.
276 T. Bui, Y. Savaria (2004). Shunt-peaking of MCML gates using active inductors. 2nd Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), p. 361-364.
277 H.T. Bui, Y. Savaria (2004). Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector. IEEE International Symposium on Circuits and Systems (ISCAS 2004), v. 4, p. 369-372.
278 H.T. Bui, Y. Savaria (2004). 10 GHz PLL using active shunt-peaked MCML gates and improved frequency acquisition XOR phase detector in 0.18 mu m CMOS. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, p. 115-118.
279 F.-R. Boyer, H.G. Epassa, B. Pontikakis, Y. Savaria, W. Ling (2004). A variable period clock synthesis (VPCS) architecture for next-generation power-aware SoC applications. 2nd Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), p. 145-148.
280 M. Bougataya, A. Lakhasasi, Y. Savaria, D. Massicotte (2004). Thermo-mechanical stress analysis of VLSI devices by partially coupled finite element method. 18th Annual Canadian Conference on Electrical and Computer Engineering (CCEC 2004), v. 1, p. 509-513.
281 A. Boudjella, Z.F. Jin, Y. Savaria (2004). Electrical Field Analysis of Nanoscale Field Effect Transistors. Japanese Journal of Applied Physics, 43(6), p. 3831-3837.
282 J.F. Boland, A. Chureau, C. Thibeault, Y. Savaria, F. Gagnon, Z. Zilic (2004). An efficient methodology for design and verification of an equalizer for a software defined radio. 2nd Annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), p. 73-76.
283 A. Trabelsi, Y. Savaria, Y. Audet (2003). Automatic offset correction technique based on active load tuning. 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), p. 5-8.
284 B. Tohio, S. Pierre, Y. Savaria, M.M. Mbaye (2003). Protocol Convertibility in a Network Processing EnvironmentCanadian Conference on Electrical and Computer Engineering (CCECE 2003), v. 2, p. 801-804. DOI : 10.1109/CCECE.2003.1226016 
285 Y. Tang, L. Qian, Y. Wang, Y. Savaria (2003). New memory reference reduction method for FFT implementation on DSP. IEEE International Symposium on Circuits and Systems (ISCAS 2003), p. 111-116.
286 J.F. Richard, B. Lessard, R. Meingan, S. Martel, Y. Savaria (2003). High voltage interfaces for CMOS/DMOS technologies. 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), p. 93-96.
287 M. Renaud, Y. Savaria (2003). A CMOS three-state frequency detector complementary to an enhanced linear phase detector for PLL, DLL or high frequency clock skew measurement. IEEE International Symposium on Circuits and Systems (ISCAS 2003), v. 3, p. 148-151.
288 S. Regimbal, J.-F. Lemire, Y. Savaria, G. Bois, E.M. Aboulhamid, A. Baron (2003). Automating functional coverage analysis based on an executable specification. 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, p. 228-234.
289 S. Regimbal, J.F. Lemire, Y. Savaria, G. Bois, M. Aboulhamid, A. Baron (2003). Aspect Partitioning for Hardware Verification Reuse. System-on-Chip for Real-Time Applications, p. 51-60.
290 J. Pepga bissou, M. Dubois, Y. Savaria, G. Bois (2003). High speed system bus for a SoC network processing platform. 15th International Conference on Microelectronics (ICM 2003), p. 194-197.
291 P. Nsame, Y. Savaria (2003). System-level design closure. 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), p. 101-104.
292 B. Nicolescu, Y. Savaria, R. Velazco (2003). SIED: software implemented error detection18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2003), p. 589-596. DOI : 10.1109/DFTVS.2003.1250159 
293 B. Nicolescu, P. Perronnard, R. Velazco, Y. Savaria (2003). Efficiency of transient bit-flips detection by software means a complete study18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2003), p. 377-384. DOI : 10.1109/DFTVS.2003.1250134 
294 M.M. Mbaye, B. Tohio, Y. Savaria, S. Pierre (2003). Performance of a Firewire-Ethernet Protocols Conversion on an Arm7 Embedded Processor. Canadian Conference on Electrical and Computer Engineering (CCECE 2003), p. 1267-1270.
295 M. Lu, Y. Savaria, B. Qiu, J. Taillefer (2003). IEEE 1149.1 based defect and fault tolerant scan chain for water safe integration. DFT 2003, p. 18-25.
296 L. Loiseau, Y. Savaria (2003). Design reuse. System-on-chip for real-time applications. Luwer academic publishers. p. 29-82.
297 L. Loiseau, Y. Savaria (2003). Methodologies and Strategies for Effective Design-Reuse. System-on-Chip for Real-Time Applications, p. 31-40.
298 J.F. Lemire, E.M. Aboulhamid, Y. Savaria, G. Bois, A. Baron (2003). Implementing e assertion checkers from an SDL executable specifications. DVCON.
299 P.H. Lamarche, Y. Savaria (2003). VHDL source code generator and analysis tool to design linear interpolars. 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), p. 69-72.
300 H. Khali, Y. Savaria, J.L. Houle, M. Rioux, J.A. Beraldin, D. Poussart (2003). Improvement of Sensor Accuracy in the Case of a Variable Surface Reflectance Gradient for Active Laser Range Finders. IEEE Transactions on Instrumentation and Measurement, 52(6), p. 1799-1808.
301 H. Khali, Y. Savaria (2003). Hardware-software co design model for real-time 3D image computation using active laser range finders : a case study10th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2003), v. 2, p. 854-857. DOI : 10.1109/ICECS.2003.1301921 
302 Z.F. Jin, J.J. Laurin, Y. Savaria (2003). Comparison of Propagation Characteristics Between Single and Coupled Mis Interconnect Topologies in Vlsi Circuits. Canadian Conference on Electrical and Computer Engineering (CCECE 2003), p. 5-8.
303 E. Granger, Y. Savaria, P. Lavoie (2003). A Pattern Reordering Approach Based on Ambiguity Detection for Online Category Learning. IEEE Transactions on Pattern Analysis and Machine Intelligence, 25(4), p. 524-528.
304 E. Granger, S. Catudal, R. Grou, M.M. Mbaye, Y. Savaria (2003). On current strategies for hardware acceleration of digital image restoration filters. WSEAS Transactions on Electronics, 1(3), p. 551-557.
305 H. Ghattas, Y. Savaria (2003). Design of dedicated low complexity embedded processors for SOC network processing applications. 1st Annual Northeast Workshop on Circuits and Systems (NEWCAS 2003), p. 21-24.
306 H. Ghattas, M.M. Mbaye, J.B. Pepga, Y. Savaria (2003). SoC platform architecture for a network processor. International Symposium on System-on-Chip, p. 49-52.
307 N. Chabini, I. Chabini, E.M. Aboulhamid, Y. Savaria (2003). Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(3), p. 346-351.
308 N. Chabini, I. Chabini, E.M. Aboulhamid, Y. Savaria (2003). Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs. Great Lakes Symposium on VLSI (GLSVLSI 2003), p. 221-224.
309 S. Catudal, M.A. Cantin, Y. Savaria (2003). Performance driven validation applied to viseo processing. WSEAS Transactions on Electronics, 1(3), p. 568-574.
310 M. Bougataya, A. Lakhsasi, Y. Savaria, D. Massicotte (2003). Stress and distortion behavior for VLSI steady state thermal analysis. Canadian Conference on Electrical and Computer Engineering (CCECE 2003), v. 1, p. 111-116.
311 A. Boudjella, Z.F. Jin, Y. Savaria (2003). Electrical field analysis of nanoscaled field effect transistors. International Microprocesses and Nanotechnology Conference, p. 240-241.
312 J.P. Bissou, Y. Savaria (2003). Conception de haut niveau d'une plate-forme SOC pour la conversion de protocoles réseaux. Canadian Conference on Electrical and Computer Engineering (CCECE 2003), v. 2, p. 1271-1274.
313 S. Beaudin, R.J. Marceau, G. Bois, Y. Savaria, N. Kandil (2003). An Economic Parallel Processing Technology for Faster Than Real-Time Transient Stability Simulation. European Transactions on Electrical Power, 13(2), p. 105-112.
314 J.P. Bissou, M. Dubois, Y. Savaria, G. Bois (2003). High-speed system bus for a SoC network processing platform15th International Conference on Microelectronics (ICM 2003), p. 194-197. DOI : 10.1109/ICM.2003.238564 
315 M. Lu, Y. Savaria, B. Qiu, J. Taillefer (2003). IEEE 1149.1 based defect and fault tolerant scan chain for wafer scale integration18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT 2003), p. 18-25. DOI : 10.1109/DFTVS.2003.1250091 
316 M. Renaud, Y. Savaria (2002). A linear phase detector for arbitrary clock signals. IEEE International Symposium on Circuits and Systems (ISCAS 2002), v. 4, p. 775-778.
317 M. Meunier, Y. Gagnon, Y. Savaria, A. Lacourse (2002). Laser tuning silicon microdevices for analogue microelectronics. SPIE Regional Meeting on Optoelectronics, Photonics, and Imaging (Opto Canada 2002), v. TD01, p. 205-208.
318 A. Meunier, Y. Gagnon, Y. Savaria, A. Lacourse, M. Cadotte (2002). A novel laser trimming technique for microelectronics. Applied Surface Science, 186(1-4), p. 52-56.
319 L. Loiseau, Y. Savaria (2002). Methodologies and Strategies for Effective Design Reuse. Revue canadienne de génie électrique et informatique, 27(4), p. 165-169.
320 L.-P. Lafrance, M.-A. Cantin, Y. Savaria, S.H. Sung, P. Lavoie (2002). Architecture and performance characterization of hardware and software implementations of the Crozier frequency estimation algorithm. IEEE International Symposium on Circuits and Systems (ISCAS 2002), v. 4, p. 823-826.
321 Z.-F. Jin, J.-J. Laurin, Y. Savaria (2002). A practical approach to model long MIS interconnects in VLSI circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10(4), p. 494-507.
322 S. Hashemi, M. Sawan, Y. Savaria (2002). Analysis of power chains in transcutaneously powered electronic implants. 7th Annual Conference of the International Functional Electrical Stimulation Society (IFESS 2002), p. 196-198.
323 Y. Fouzar, Y. Savaria, M. Sawan (2002). A CMOS phase-locked loop with an auto-calibrated VCO. IEEE International Symposium on Circuits and Systems (ISCAS 2002), v. 3, p. 177-180.
324 J. Dido, N. Geraudie, L. Loiseau, O. Payeur, Y. Savaria, D. Poirier (2002). A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs. 10th ACM International Symposium on Field-Programmable Gate Arrays (FPGA 2002), p. 50-55.
325 N. Chabini, E.M. Aboulhamid, I. Chabini, Y. Savaria (2002). Minimizing the Number of Phases in Clocked Digital Designs Derived Using Modulo Scheduling Techniques. 14th International Conference on Microelectronics (ICM 2002), p. 92-95.
326 M.-A. Cantin, Y. Savaria, P. Lavoie (2002). A comparison of automatic word length optimization procedures. IEEE International Symposium on Circuits and Systems (ISCAS 2002), v. 2, p. 612-615.
327 D.E. Calbaza, Y. Savaria (2002). A Direct Digital Period Synthesis Circuit. IEEE Journal of Solid-State Circuits, 37(8), p. 1039-1045.
328 A. Bendali, Y. Savaria (2002). Low-voltage bandgap reference with temperature compensation based on a threshold voltage technique. IEEE International Symposium on Circuits and Systems (ISCAS 2002), v. 3, p. 201-204.
329 L. Thériault, D. Audet, Y. Savaria (2001). Performance estimators for hardware/software co-design. IEEE International Symposium on Circuits and Systems (ISCAS 2001), v. 5, p. 17-20.
330 M. Nekili, Y. Savaria, G. Bois (2001). Minimizing process-induced skew using elay tuning. IEEE International Symposium on Circuits and Systems (ISCAS 2001), v. 4, p. 426-429.
331 G. Monte, B. Antaki, S. Patenaude, Y. Savaria, C. Thibeault, P. Trouborst (2001). Tools for the characterization of bipolar CML testability. 19th IEEE VLSI Test Symposium (VTS 2001), p. 388-395.
332 M. Meunier, Y. Gagnon, Y. Savaria, A. Lacourse, M. Cadotte (2001). A novel laser trimming technique for microelectronics. 6th Conference on Laser Applications in Microelectronic and Optoelectronic Manufacturing (LAMOM 2001), v. 4274 (Proceedings of SPIE), p. 385-392.
333 É. Granger, Y. Savaria, P. Lavoie (2001). A pattern reordering approach based on ambiguity detection for on-line category learning. (Rapport 01-02). 40 pages.
334 Y. Gagnon, M. Meunier, Y. Savaria (2001). Method and apparatus for iteratively, selectively tuning the impedance of integrated semiconductor devices using a focussed heating source. (No de brevet - US 6329272).
335 Y. Fouzar, Y. Savaria, M. Sawan (2001). A new controlled gain phase-locked loop technique. IEEE International Symposium on Circuits and Systems (ISCAS 2001), v. 4, p. 810-813.
336 N. Chabini, Y. Savaria (2001). Methods for optimizating register placement in synchronous circuits derived using software pipelining techniques. 14th International Symposium on System Synthesis (ISSS 2001), p. 209-214.
337 N. Chabini, M. Aboulhamid, Y. Savaria (2001). Efficient methods for reducing register and phase requirements for synchronous circuits derived using software pipeling techniques. European Conference on Circuit Theory and Design, v. 2, p. 237-240.
338 N. Chabini, M. Aboulhamid, Y. Savaria (2001). Determining schedules for reducing power consuption using mulyiple supply voltages. International Conference on Computer Design (ICCD 2001), p. 546-552.
339 N. Chabini, E.M. Aboulhamid, Y. Savaria (2001). Reducing register and phase requirements for synchronous circuits derived using software pipeling techniques. IEEE Computer Society Workshop on VLSI (WVLSI 2001), p. 71-77.
340 N. Chabini, E.M. Aboulhamid, Y. Savaria (2001). Fast method for determining an efficient bound on the optimal solution of the cost-to-time ratio problem. 5th World Multiconference on Systemics, Cybernetics and Informatics (SCI 2001) and 7th International Conference in Information Systems Analysis and Synthesis (ISAS 2001), v. VII, p. 195-200.
341 N. Chabini, E.M. Aboulhamid, Y. Savaria (2001). Minimizing registe requirements for synchronous circuits derived using software pipelining techniques. 13th International Conference on Microelectronics (ICM 2001), p. 249-252.
342 M.-A. Cantin, Y. Savaria, D. Prodanos, P. Lavoie (2001). An automatic word length determination method. IEEE International Symposium on Circuits and Systems (ISCAS 2001), v. 5, p. 53-56.
343 D.E. Calbaza, Y. Savaria (2001). Direct Digital Frequency Synthesis of Low-Jitter Clocks. IEEE Journal of Solid-State Circuits, 36(3), p. 570-572.
344 F.R. Boyer, E.M. Aboulhamid, Y. Savaria, M. Boyer (2001). Optimal Design of Synchronous Circuits Using Software Pipelining Techniques. ACM Transactions on Design Automation of Electronic Systems, 6(4), p. 516-532.
345 N. Chabini, E.M. Aboulhamid, Y. Savaria (2001). Reducing register and phase requirements for synchronous circuits derived using software pipelining techniquesIEEE Computer Society Workshop on VLSI (WVLSI 2001), p. 71-77. DOI : 10.1109/IWV.2001.923142 
346 P. Vado, Y. Savaria, Y. Zoccarato, C. Robach (2000). A methodology for validating digital circuits with mutation testing. IEEE International Symposium on Circuits and Systems (ISCAS 2000), p. 343-346.
347 F. Planque, I. Kraljic, Y. Savaria (2000). Mapping irregular algorithms in a custom computing image processing framework. 3rd Annual Military and Aerospace Applications of Programmable Devices and Technologies International Conference (MAPLD 2000).
348 P. Nsame, R. Grou-Szabo, Y. Savaria (2000). INTIME: a multi-tool specification environment for ensuring timing constraints integrity for SOC design. IP Based Design 2000, p. 139-144.
349 O. Hébert, I.C. Kraljic, Y. Savaria (2000). A method to derive application-specific embedded processing cores. 8th International Workshop on Hardware/Software Codesign (CODES 2000), p. 88-92.
350 Y. Fouzar, M. Sawan, Y. Savaria (2000). CMOS Wide-Swing Differential VCO for Fully Integrated Fast PLL. 43rd IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2000), p. 948-950.
351 Y. Fouzar, M. Sawan, Y. Savaria (2000). A new fully integrated CMOS phase-locked loop with low jitter and fast lock time. IEEE International Symposium on Circuits and Systems (ISCAS 2000), v. 2, p. 253-256.
352 Y. Fouzar, M. Sawan, Y. Savaria (2000). Very short locking time PLL based on controlled gain technique. 7th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2000), p. 252-255.
353 C. Donfack, M. Sawan, Y. Savaria (2000). Fully integrated AC impedance measurement technique for implantable electrical stimulation applications. 5th Annual Conference of the International Functional Electrical Stimulation Society (IFESS 2000).
354 C. Donfack, M. Sawan, Y. Savaria (2000). Techniques de caractérisation de l'interface électrode-tissus. 2nd Symposium on Advanced Biomaterials (ISAB 2000).
355 C. Donfack, M. Sawan, Y. Savaria (2000). Implantable Measurement Technique Dedicated to the Monitoring of Electrode-Nerve Contact in Bladder Stimulators. Medical & Biological Engineering & Computing, 38(4), p. 465-468.
356 M.-A. Cantin, Y. Blaquière, Y. Savaria, P. Lavoie, É. Granger (2000). Analysis of quantization effects in a digital hardware implementation of a fuzzy ART neural network algorithm. IEEE International Symposium on Circuits and Systems (ISCAS 2000), v. 3, p. 141-144.
357 D.E. Calbaza, Y. Savaria (2000). Jitter model of direct digital synthesis clock generators. TCAS-I 2000.
358 D.E. Calbaza, Y. Savaria (2000). Direct digital frequency synthesis of low-jitter clocks. IEEE Custom Integrated Circuits Conference, p. 31-34.
359 D.E. Calbaza, Y. Savaria (2000). A direct digitally delay generator. 23rd International Semiconductor Conference (CAS 2000), p. 87-90.
360 F.R. Boyer, E.M. Aboulhamid, Y. Savaria (2000). Efficient verification method for a class of multi-phase sequential circuits. 7th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2000), p. 510-515.
361 S.M.I. Adham, Y. Savaria, B. Antaki, N. Xiong (2000). Voltage excursion detection apparatus. (No de brevet - US 6100716).
362 P. Nsame, Y. Savaria (1999). Virtualising on-chip bus interfaces for improved embedded processor system performance. IFIP International Workshop on IP Based Synthesis and System Design, p. 138-143.
363 M. Nekili, Y. Savaria, G. Bois (1999). Spatial Characterization of Process Variations Via Mos Transistor Time Constants in Vlsi and Wsi. IEEE Journal of Solid-State Circuits, 34(1), p. 80-84.
364 B. Le Chapelain, A. Mechain, Y. Savaria, G. Bois (1999). Development of a high performance TSPC library for implementation of large digital building blocks. IEEE International Symposium on Circuits and Systems (ISCAS 1999), v. 1, p. 443-446.
365 P. Lavoie, J.F. Crespo, Y. Savaria (1999). Generalization, Discrimination, and Multiple Categorization Using Adaptive Resonance Theory. IEEE Transactions on Neural Networks, 10(4), p. 757-767.
366 Z.-F. Jin, J.-J. Laurin, Y. Savaria (1999). New approach to analyze interconnect delays in RC wire models. IEEE International Symposium on Circuits and Systems (ISCAS 1999), v. 6, p. 246-249.
367 Y. Jiang, Y. Tang, Y. Wang, Y. Savaria (1999). Evaluating the ouptput probability of boolean functions without floating point operations. Canadian Conference on Electrical and Computer Engineering (CCECE 1999), p. 433-437.
368 C. Donfack, M. Sawan, Y. Savaria (1999). Efficient monitoring of electrodes-nerve contacts during FNS of the bladder. 4th Annual Conference of the International Functional Electrical Stimulation Society (IFESS 1999).
369 C. Cousineau, F. Laperle, Y. Savaria, K.L. Pocek, J.M. Arnold (1999). Design of a JTAG based run time reconfigurable system. 7th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p. 268-269.
370 D.E. Calbaza, Y. Savaria (1999). Jitter model of direct digital synthesis clock generators. IEEE International Symposium on Circuits and Systems (ISCAS 1999), v. 1, p. 1-4.
371 B. Bosi, G. Bois, Y. Savaria (1999). Reconfigurable Pipelined 2-D Convolvers for Fast Digital Signal Processing. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 7(3), p. 299-308.
372 B. Antaki, Y. Savaria, A. Saman, N. Xiong, D. Borrione, R. Ernst (1999). Design for testability method for CML digital circuits. Design, Automation and Test in Europe Conference and Exhibition (DATE 1999), p. 360-367.
373 Y. Savaria, F. El Hassan, H. Khali, M. Sawan (1998). Effective hardware/software implementation of a viterbi decoder using an FPGA-based reconfigurable computing platform. FDP 1998, p. 161-165.
374 Y. Savaria (1998). Study of neural networks for clustering radar signals: Final report. (Rapport 98-610). 180 pages.
375 P. Poire, Y. Savaria, H. Daniel, M.a. Cantin, Y. Blaquiere (1998). Hardware/software codesign of a Fuzzy ART neural clusterer : The benefits of configurable computing. 3rd Conference on Configurable Computing, v. 3526 (Proceedings of SPIE), p. 90-96.
376 P. Poire, M.-A. Cantin, H. Daniel, Y. Blaquiere, Y. Savaria, K.L. Pocek, J.M. Arnold (1998). A comparative analysis of fuzzy ART neural network implementations: the advantages of reconfigurable computing. IEEE Symposium on FPGAs for Custom Computing Machines, p. 304-305.
377 M. Nekili, Y. Savaria, G. Bois, M.A. Bayoumi, G. Jullien (1998). Design of clock distribution networks in presence of process variations. 8th Great Lakes Symposium on VLSI, p. 95-102.
378 P. Marriott, I. Kraljic, Y. Savaria (1998). Parallel ultra large scale engine SIMD architectures for real time digital signal processing applications. International Conference on Computer Design (ICCD 1998), p. 482-487.
379 É. Granger, Y. Savaria, P. Lavoie, M.A. Cantin (1998). Comparison of Self-Organizing Neural Networks for Fast Clustering of Radar Pulses. Signal Processing, 64(3), p. 249-269.
380 Y. Fouzar, M. Sawan, Y. Savaria (1998). A BiCMOS wide-lock range fully integrated PLL. 10th International Conference on Microelectronics, p. 274-277.
381 N. Chabini, I.E. Bennour, E.M. Aboulhamid, Y. Savaria (1998). Static method for system performance estimation. 10th International Conference on Microelectronics.
382 M.-A. Cantin , Y. Blaquière, Y. Savaria, E. Granger, P. Lavoie (1998). Implementation fo the Fuzzy ART neural network for fast clustering of radar pulses. IEEE International Symposium on Circuits and Systems (ISCAS 1998), p. 14-17.
383 F.R. Boyer, E.M. Abiylhamid, Y. Savaria, I.E. Bennour (1998). Optical design of synchronous circuits using software pipeling techniques. VLSI in Computers and Processors, p. 62-67.
384 D. Audet, S. Masson, Y. Savaria (1998). Reducing fault sensitivity of microprocessor-based system by modifying workload structure. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, p. 241-249.
385 F. Pera, Y. Savaria, G. Bois (1997). Time delay measurement methods for integrated transmission lines and high speed cells characterization. IEEE International Symposium on Circuits and Systems (ISCAS 1997), p. 293-296.
386 M. Nekili, G. Bois, Y. Savaria (1997). Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 5(2), p. 161-174.
387 P. Lavoie, J.F. Crespo, Y. Savaria (1997). Multiple categorization using fuzzy ART. IEEE International Conference on Neural Networks (ICNN 1997), p. 1983-1988.
388 H. Khali, Y. Savaria, J.L. Houle (1997). Computational limits of homogeneous acceleration using lookup tables. 11th Annual International Symposium on High Performance Computing Systems, p. 345-351.
389 M. Kafrounni, C. Thibeault, Y. Savaria (1997). Cost model for VLSI/MCM systems. IEEE Symposium on Defect and Fault Tolerance in VLSI Systems, p. 148-156.
390 R. Hrytzak, Y. Savaria, G. Goslin (1997). Reconfigurable computing greatly simplifies system development. DSP World Spring Design Conference, p. 271-286.
391 É. Granger, Y. Savaria, V. Blaquière, M.-A. Cantin, P. Lavoie (1997). A VLSI architecture for fast clustering with fuzzy ART neural networks. Journal of Microelectronic Systems Integration, 5(1), p. 3-18.
392 Y. Gagnon, Y. Savaria, M. Meunier, C. Thibeault (1997). Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1997), p. 157-165.
393 Y. Gagnon, M. Meunier, Y. Savaria, C. Thibeault (1997). Mathematical cost model for redundant multi-processor arrays. Journal of Microelectronic Systems Integration, 5(4), p. 199-208.
394 G. Bois, B. Bosi, Y. Savaria (1997). High performance reconfigurable coprocessor for digital signal processing. 14th Annual International Conference of the Mentor Graphics Users' Group.
395 N. Bélanger, B. Antaki, Y. Savaria (1997). An algorithm for fast array transfers. 11th Annual International Symposium on High Performance Computing Systems, p. 117-126.
396 B. Antaki, S. Patenaude, L. Trognon, Y. Savaria (1997). Study on split-output TSPC CMOS circuits. IEEE International Symposium on Circuits and Systems (ISCAS 1997), p. 1892-1895.
397 R. St-Amand, M. Sawan, Y. Savaria (1996). Design and optimization of a low DC offset CMOS current-source dedicated to implantable miniaturized stimulators. Analog Integrated Circuits and Signal Processing, 11(1), p. 47-61.
398 M. Soufi, S. Rochon, Y. Savaria, B. Kaminska (1996). Design and performance of CMOS TSPC cells for high speed pseudo random testing. 14th IEEE VLSI Test Symposium, p. 368-373.
399 Y. Savaria, C. Thibeault, A. Ivanov (1996). Ieee vlsi test symposium - meeting the quality challenge. IEEE Design & Test of Computers, 13(3), p. 110-112.
400 Y. Savaria, G. Bois, P. Popovic, A. Wayne (1996). Computational acceleration methodologies: advantages of reconfigurable acceleration subsystems. High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic, v. 2914 (Proceedings of SPIE), p. 195-205.
401 S. Lejmi, G. Bois, Y. Savaria (1996). On the effects of retiming applied to self-checking sequential circuit. 2nd IEEE On-Line Testing Workshop, p. 96-99.
402 P. Lavoie, J.-F. Crespo, Y. Savaria (1996). On the stability of Fuzzy ART. 18th Biennal Symposium on Communications, p. 185-188.
403 É. Granger, Y. Blaquière, Y. Savaria, M.-A. Cantin, P. Lavoie (1996). VLSI architecture for fast clustering with fuzzy ART neural networks. 1st International Workshop on Neural Networks for Identification, Control, Robotics, and Signal/Image Processing (NICROSP 1996), p. 117-125.
404 Y. Blaquiere, M. Dagenais, Y. Savaria (1996). Timing analysis speed-up using a hierarchical and a multimode approach. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(2), p. 244-255.
405 A. Belhaouane, Y. Savaria, B. Kaminska, D. Massicotte (1996). Reconstruction method for jitter tolerant data acquisition system. Journal of Electronic Testing: Theory and Applications, 9(1-2), p. 177-185.
406 A. Belhaouane, Y. Savaria, B. Kaminska (1996). Reconstruction method for data acquisition systems qith randomly distributed jitter. 2nd IEEE International Mixed Signal Testing Workshop, p. 119-122.
407 N.-E. Belabbes, A.J. Guterman, Y. Savaria, M. Dagenais (1996). Ratioed voter circuit for testing and fault-tolerance in VLSI processing arrays. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 43(2), p. 143-152.
408 D. Audet, N. Gagnon, Y. Savaria (1996). Implementing fault injection and tolerance mechanisms in multiprocessor systems. IEEE Workshop on Defect and Fault Tolerance in VLSI (DFT 1996), p. 310-317.
409 D. Audet, F. Gagnon, Y. Savaria (1996). Quantitative comparisons of TMR implementations in a multiprocessor system. 3rd IEEE On-Line Testing Workshop, p. 196-199.
410 A. Abderrahman, Y. Savaria, B. Kaminska (1996). Analyse, estimation et réduction du bruit de commutation simultanee. Revue canadienne de génie électrique et informatique, 21(4), p. 133-143.
411 C. Thibeault, Y. Savaria, J.L. Houle (1995). Equivalence proofs of some yield modeling methods for defect-tolerant integrated-circuits. IEEE Transactions on Computers, 44(5), p. 724-728.
412 M. Soufi, Y. Savaria, B. Kaminska (1995). On Using partial reset for pseudo-random testing. IEEE International Symposium on Circuits and Systems (ISCAS 1995), p. 949-952.
413 M. Soufi, Y. Savaria, B. Kaminska (1995). On the design of at-speed testable VLSI circuits. 13th IEEE VLSI Test Symposium, p. 290-295.
414 M. Soufi, Y. Savaria, F. Darlay, B. Kaminska (1995). Producing reliable initialization and test of sequential circuits with pseudorandom vectors. IEEE Transactions on Computers, 44(10), p. 1251-1256.
415 M. Sawan, R. St-Amand, Y. Savaria (1995). Design and optimization of programmable biphasic current-sources. 2nd Annual International Conference on Electronics, Circuits and Systems (ICECS 1995), p. 169-173.
416 J. Rzeszut, B. Kaminska, Y. Savaria (1995). New method for testing mixed analog and digital circuits. 4th Asian Test Symposium, p. 127-132.
417 H. Khali, Y. Savaria, J.L. Houle, J.A. Beraldin, F. Blais, M. Rioux (1995). VLSI chip for 3-D camera calibration. Canadian Conference on Electrical and Computer Engineering (CCECE 1995), p. 120-123.
418 R. Kermouche, D. Audet, Y. Savaria (1995). On the optimization of integrated hierarchical bus architectures to achieve efficient fault-tolerance. Journal of Microelectronic Systems Integration, 3(1), p. 47-63.
419 A. Gadiri, Y. Savaria, B. Kaminska (1995). Optimized CMOS compatible photoreceiver. Canadian Conference on Electrical and Computer Engineering (CCECE 1995), p. 211-214.
420 T. Blaquiere, G. Gagné, Y. Savaria, C. Evequoz (1995). A new efficient algorithmic-based seu tolerant system architecture. IEEE Transactions on Nuclear Science, 42(6), p. 1599-1606.
421 J. Belzile, Y. Savaria, D. Haccoun, M. Chalifoux (1995). Bounds on the performance of partial selection networks. IEEE Transactions on Communications, 43(2-4), p. 1800-1809.
422 A. Barwicz, D. Massicotte, Y. Savaria, P.A. Pango, R.Z. Morawski (1995). An application-specific processor dedicated to kalman-filter-based correction of spectrometric data. IEEE Transactions on Instrumentation and Measurement, 44(3), p. 720-724.
423 D. Audet, Y. Savaria, N. Arel (1995). Effective ultra large scale integration (ULSI) architecture techniques: FATMOS, a fault-tolerant multiprocessor operating system. 36 pages.
424 D. Audet, Y. Savaria (1995). High-speed interconnections using true single-phase clocking. Journal of Microelectronic Systems Integration, 3(4), p. 247-257.
425 D. Audet, Y. Savaria (1995). Effective ultra large scale integration (ULSI) architecture techniques : the routers, from a functional to a detailed implementation description. 123 pages.
426 D. Audet, Y. Savaria (1995). Effective ultra large scale integration (ULSI) architecture techniques : the host interface. 61 pages.
427 D. Audet, Y. Savaria (1995). High-speed interconnections using true single-phase clocking. 7th IEEE Annual International Conference on Wafer Scale Integration, p. 258-267.
428 C. Thibeault, Y. Savaria, J.L. Houle (1994). A fast method to evaluate the optimum number of spares in defect-tolerant integrated-circuits. IEEE Transactions on Computers, 43(6), p. 687-697.
429 R. St-Amand, Y. Savaria, M. Sawan (1994). Design optimization of a current source for microstimulator applications. 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), p. 129-132.
430 R. St.-Amand, M. Sawan, Y. Savaria (1994). Generation of balanced bipolar stimuli based on current sources without coupling capacitor. 16th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC 1994), v. 2, p. 992-993.
431 Y. Savaria, D. Chtchvyrkov, J.F. Currie (1994). Fast CMOS voltage-controlled ring oscillator. IEEE International Symposium on Circuits and Systems (ISCAS 1994), p. 359-362.
432 Y. Savaria (1994). Parallel microprocessor architecture. (No de brevet - US 5276893).
433 M. Nekili, Y. Savaria, G. Bois (1994). Fast low-power driver for long interconnections in VLSI systems. IEEE International Symposium on Circuits and Systems (ISCAS 1994), v. 4, p. 343-346.
434 M. Nekili, Y. Savaria, G. Bois (1994). A variable-size parallel regenerator for long integrated interconnections. 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), v. 1, p. 50-53.
435 M. Nekili, G. Bois, Y. Savaria (1994). Deterministic skew modeling and high-speed clocking of large integrated systems by using logic-based & hybrid H-trees. (Rapport 94-09). 46 pages.
436 P. Lavoie, D. Haccoun, Y. Savaria (1994). Systolic architecture for fast stack sequential decoders. IEEE Transactions on Communications, 42(2/3/4, pt. 1), p. 324-335.
437 S.M. Kroumba, G. Bois, Y. Savaria (1994). Synthesis approach for the generation of parallel architectures. 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), p. 323-326.
438 R. Kermouche, Y. Savaria, D. Audet (1994). Harvest model of an integrated hierarchical-bus architecture. 6th Annual IEEE International Conference on Wafer Scale Integration, p. 69-78.
439 R. Kermouche, Y. Savaria (1994). Defect and fault tolerant scan chains. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1994), p. 185-193.
440 S. Ghannoum, D. Chtchvyrkov, Y. Savaria (1994). Comparative study of single-phase clocked latches using estimation criteria. IEEE International Symposium on Circuits and Systems (ISCAS 1994), p. 347-350.
441 S. Ghannoum, D. Chtchvyrkov, Y. Savaria (1994). Single-clock dynamic latches optimization. 37th Midwest Symposium on Circuits and Systems (MWSCAS 1994), p. 46-49.
442 J.-F. Crespo, P. Lavoie, Y. Savaria (1994). Fast convergence with low precision weights in ART1 networks. IEEE International Symposium on Circuits and Systems (ISCAS 1994), p. 237-240.
443 N. BenHamida, B. Kaminska, Y. Savaria (1994). Pseudo-random vector compaction for sequential testability. IEEE International Symposium on Circuits and Systems (ISCAS 1994), p. 63-66.
444 N. Bélanger, D. Haccoun, Y. Savaria (1994). A multiprocessor architecture for multiple path stack sequential decoders. IEEE Transactions on Communications, 42(2-4, pt.2), p. 951-957.
445 A. Barwicz, D. Massicotte, Y. Savaria, M.A. Santerre, R.Z. Morawski (1994). An integrated structure for kalman-filter-based measurand reconstruction. IEEE Transactions on Instrumentation and Measurement, 43(3), p. 403-410.
446 A. Barwicz, D. Massicotte, Y. Savaria, M.A. Santerre, R.Z. Morawsi (1994). Application-specific processor dedicated to Kalman-filter-based correction od spectrometric data. IEEE Instrumentation and Measurement Technology Conference (IMTC 1994), p. 352-356.
447 D. Audet, Y. Savaria, N. Arel (1994). Architectural approach for increasing clock frequency and communication speed in monolithic-WSI systems. 6th Annual IEEE International Conference on Wafer Scale Integration, p. 235-243.
448 D. Audet, Y. Savaria, N. Arel (1994). Pipelining communications in large VLSI/ULSI systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2(1), p. 1-10.
449 D. Audet, Y. Savaria (1994). Architectural approach for increasing clock frequency and communication speed in momolithic WSI systems. IEEE Transactions on Components Packaging and Manufacturing Technology. Part B, Advanced Packaging, 17(3), p. 362-368.
450 A. Abderrahman, B. Kaminska, Y. Savaria (1994). Estimation of simultaneous switching power and ground noise of static CMOS combinational circuits. European Design and Test Conference, p. 658.
451 J. Crepeau, C. Thibeault, Y. Savaria (1993). Some results on yield and local design rule relaxationIEEE International Workshop on Defect and Fault Tolerance in VLSI Systems (DFT 1993), p. 144-151. DOI : 10.1109/DFTVS.1993.595745 

 

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