Benacer, I., Boyer, F.-R., & Savaria, Y. (2019). A high-speed, scalable, and programmable traffic manager architecture for flow-based networking. IEEE Access, 7, 2231-2243.
Directory of Experts
Boyer, François-Raymond
Directory of Experts
Boyer, François-Raymond
Directory of Experts
Publications by type
Journal article (7)
Conference paper (33)
Book
Book chapter (2)
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Report (1)
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François-Raymond Boyer (43)
- Journal articles (7)
- 2019
Journal article Journal article Benacer, I., Boyer, F.-R., & Savaria, Y. (2019). HPQS: A fast, high-capacity, hybrid priority queuing system for high-speed networking devices. IEEE Access, 7, 130672-130684.
- 2018
Journal article Benacer, I., Boyer, F.-R., & Savaria, Y. (2018). A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 26(10), 1939-1952.
- 2012
Journal article Siadjine Njinowa, M., Tien Bui, H., & Boyer, F.-R. (2012). Novel Threshold-Based Standard-Cell Flash ADC. Circuits and Systems, 3(1), 29-34.
- 2011
Journal article Hosseini, P., Martins, S., Martin, T., Radziszewski, P., & Boyer, F.-R. (2011). Acoustic emissions simulation of tumbling mills using charge dynamics. Minerals Engineering, 24(13), 1440-1447.
- 2006
Journal article Boyer, F.-R., Epassa, H. G., & Savaria, Y. (2006). Embedded power-aware cycle by cycle variable speed processor. IEE Proceedings. Computers and Digital Techniques, 153(4), 283-290.
- 2001
Journal article Boyer, F.-R., Aboulhamid, E. M., Savaria, Y., & Boyer, M. (2001). Optimal Design of Synchronous Circuits Using Software Pipelining Techniques. ACM Transactions on Design Automation of Electronic Systems, 6(4), 516-532.
- 2019
- Conference papers (33)
- 2019
Conference paper Santiago Da Silva, J., Boyer, F.-R., & Langlois, J. M. P. (2019, April). Module-per-object: A human-driven methodology for c++-based high-level synthesis design [Paper]. 27th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2019), San Diego, CA, United states.
- 2018
Conference paper Benacer, I., Boyer, F.-R., & Savaria, Y. (2018, May). Design of a low latency 40 Gb/s flow-based traffic manager using high-level synthesis [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy (5 pages).Conference paper Santiago da Silva, J., Boyer, F.-R., Chiquette, L.-O., & Langlois, J. M. P. (2018, June). Extern objects in P4: an ROHC compressing scheme case study [Paper]. IEEE Conference on Network Softwarization (NetSoft 2018), Montréal, Québec.Conference paper Benacer, I., Boyer, F.-R., & Savaria, Y. (2018, June). HPQ: a high capacity hybrid priority queue architecture for high-speed network switches [Paper]. 16th IEEE International New Circuits and Systems Conference (NEWCAS 2018), Montréal, Québec.Conference paper Santiago da Silva, J., Boyer, F.-R., & Langlois, J. M. P. (2018, February). P4-compatible high-level synthesis of low latency 100 Gb/s streaming packet parsers in FPGAs [Paper]. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2018), Monterey, California, USA.
- 2017
Conference paper Benacer, I., Boyer, F.-R., & Savaria, Y. (2017, June). A high-speed traffic manager architecture for flow-based networking [Paper]. 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France.
- 2016
Conference paper Benacer, I., Boyer, F.-R., Bélanger, N., & Savaria, Y. (2016, June). A fast systolic priority queue architecture for a flow-based Traffic Manager [Paper]. 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages).Conference paper Lacroix, A. B., Langlois, J. M. P., Boyer, F.-R., Gosselin, A., & Bois, G. (2016, March). Node configuration for the Aho-Corasick algorithm in intrusion detection systems [Poster]. ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2016), Santa Clara, Californie (2 pages).Conference paper Alizadeh, R., Belanger, N., Savaria, Y., & Boyer, F.-R. (2016, June). Performance characterization of an SCMA decoder [Paper]. 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages).
- 2013
Conference paper Njinowa, M. S., Bui, H. T., & Boyer, F.-R. (2013, June). Design of low power 4-bit flash ADC based on standard cells [Paper]. 11th IEEE International New Circuits and Systems Conference (NEWCAS 2013), Paris, France (4 pages).
- 2010
Conference paper Njinowa, M. S., Bui, H. T., & Boyer, F.-R. (2010, May). Peak-to-peak jitter reduction technique for the Free-Running Period Synthesizer (FRPS) [Paper]. IEEE International Symposium on Circuits and Systems. ISCAS 2010, Paris, France.
- 2009
Conference paper Njinowa, M. S., Bui, H. T., & Boyer, F.-R. (2009, June). Design and optimization of a low complexity all-digital digital-to-analog converter [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France.Conference paper Vezant, B., Mansuy, C., Bui, H. T., & Boyer, F.-R. (2009, June). Direct digital synthesis-based all-digital phase-locked loop [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France.Conference paper Trabelisi, A., Boyer, F.-R., & Boukadoum, M. (2009, December). Robust Estimation of LP Parameters in White Noise with Unknown Variance [Paper]. 16th IEEE International Conference on Electronics, Circuits and Systems, Medina, Tunisia.
- 2008
Conference paper Pontikakis, B., Bui, H. T., Boyer, F.-R., & Savaria, Y. (2008, June). A novel phase-locked loop (PLL) architecture without an analog loop filter for better integration in ultra-deep submicron SoCs [Paper]. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008).
- 2007
Conference paper Pontikakis, B., Bui, H. T., Boyer, F.-R., & Savaria, Y. (2007, May). A low-complexity high-speed clock generator for dynamic frequency scaling of FPGA and standard-cell based designs [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, Louisiana.Conference paper Trabelisi, A., Boyer, F.-R., Savaria, Y., & Boukadoum, M. (2007, August). Improving LPC Analysis of Speech in Additive Noise [Paper]. IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Québec.Conference paper Trabelisi, A., Boyer, F.-R., Savaria, Y., & Boukadoum, M. (2007, December). Iterative Noise-Compensated Method to Improve LPC Based Speech Analysis [Paper]. 14h IEEE International Conference on Electronics, Circuits & Systems, Marrakech, Morocco.Conference paper Pontikakis, B., Boyer, F.-R., Savaria, Y., & Bui, H. T. (2007, August). Precise free-running period synthesizer (FRPS) with process and temperature compensation [Paper]. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007).Conference paper Trabelsi, A., Boyer, F.-R., & Savaria, Y. (2007, August). Speech enhancement based noise PSD estimator to remove cosine shaped residual noise [Paper]. 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007).
- 2006
Conference paper Pontikakis, B., Boyer, F.-R., & Savaria, Y. (2006, May). A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece.
- 2005
Conference paper Epassa, H. G., Boyer, F.-R., & Savaria, Y. (2005, May). Implementation of a Cycle by Cycle Variable Speed Processor [Paper]. IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan.Conference paper Pontikakis, B., Boyer, F.-R., & Savaria, Y. (2005, July). Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period [Paper]. 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005), Banff, Alberta, Canada.
- 2004
Conference paper Boyer, F.-R., Epassa, H. G., Pontikakis, B., Savaria, Y., & Ling, W. (2004, June). A variable period clock synthesis (VPCS) architecture for next-generation power-aware SoC applications [Paper]. 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal, Québec.Conference paper Lapalme, J., Aboulhamid, E. M., Nicolescu, G., Charest, L., Boyer, F.-R., David, J. P., & Bois, G. (2004, February). [dot]Net framework - A solution for the next generation tools for system-level modeling and simulation [Paper]. Design, Automation and Test in Europe Conference and Exhibition (DATE 2004), Paris, France.Conference paper Lapalme, J., Aboulhamed, E. M., Nicolescu, G., Charest, L., Boyer, F.-R., David, J. P., & Bois, G. (2004, June). Esys.net: A New Solution for Embedded Systems Modeling and Simulation [Paper]. ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES 2004), Washington, D.C.. Published in ACM Sigplan Notices, 39(7).Conference paper Benny, O., Rondonneau, M., Chevalier, J., Bois, G., Aboulhamid, E. M., & Boyer, F.-R. (2004, March). SoC software refinement approach for a systemC platform [Paper]. Design & Verification Conference & Exhibition (DVCon 2004), San Jose, California.
- 2003
Conference paper Boyer, F.-R., Yang, L., Aboulamid, E. M., Charest, L., & Nicolescu, G. (2003, December). Multiple SimpleScalar Processors with Introspection, under SystemC [Paper]. 46th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2003), Cairo, Egypt.
- 2002
Conference paper Li, J., Boyer, F.-R., & Aboulhamid, E. M. (2002, July). Retargetable C Compiler for Network Processors [Paper]. 6th World Multiconference on Systemics, Cybernetics and Informatics, Orlando, Florida.
- 2001
Conference paper Boyer, F.-R., Aboulhamid, E. M., & Savaria, Y. (2001, August). Minimizing sensitivity to clock skew variations using level sensitive latches [Paper]. 15th European Conference on Circuit Theory and Design (ECCTD 2001), Espoo, Finland.Conference paper Martins, S., Hosseini, P., Martin, T., Radziszewski, P., Boyer, F.-R., Faucher, A., Makni, S., & Sabih, A. (2001, September). Simulating tumbling mill acoustic signals using DEM [Paper]. 5th International Conference on Autogenous and Semiautogenous Grinding Technology (SAG 2011), Vancouver, B.C..
- 2000
Conference paper Boyer, F.-R., Aboulhamid, E. M., & Savaria, Y. (2000, January). Efficient verification method for a class of multi-phase sequential circuits [Paper]. 7th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2000).
- 1996
Conference paper Cloutier, J., Cosatto, E., Pigeon, S., Boyer, F.-R., & Simard, G. (1996, February). VIP: an FPGA-based processor for image processing and neural networks [Paper]. 5th International Conference on Microelectronics for Neural Networks, Lausanne, Switzerland.
- 2019
- Book chapters (2)
- 2012
Book chapter Trabelsi, A., Boyer, F.-R., & Savaria, Y. (2012). Real-time dual-microphone speech enhancement. In Ramakrishnan, S. (ed.), Speech Enhancement, Modeling and Recognition - Algorithms and Applications (19-34).
- 2004
Book chapter Chevalier, J., Benny, O., Rondonneau, E. M., Bois, G., & Boyer, F.-R. (2004). SPACE : a hardware/software system C modeling platform including and RTOS. In Languages for System Specification : Selected Contributions on UML, SystemC, System Verilog, Mixed-Signal Systems, and Property Specification from FDL'03 (91-104).
- 2012
- Reports (1)
- 2006
Report Trabelsi, A., Boyer, F.-R., & Savaria, Y. (2006). On the application of minimum noise tracking to cancel cosine shaped residual noise. (Technical Report n° EPM-RT-2006-09).
- 2006
