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Photo de Yvon Savaria

Yvon Savaria

Professeur titulaire et directeur
Département de génie électrique

Publications à Polytechnique

Ces données sont extraites du Répertoire des publications de l'École Polytechnique de Montréal. La liste ci-dessous contient seulement les publications auxquelles a participé le professeur ou le chercheur depuis son entrée en fonction à l’École. De plus, certaines publications ne sont pas dans cette liste, notamment les notes de cours et les rapports techniques internes plus d'information...

1Al-Bayati, Z., Ait Mohamed, O., Hasan, S.R., Savaria, Y. (2012). A Novel Hybrid FIFO Asynchronous Clock Domain Crossing Interfacing Method. 22nd Great Lakes Symposium on VLSI, GLSVLSI'2012, p. 271-274. 
2Mbaye, M.M., Belanger, N., Savaria, Y., Pierre, S. (2012). Loop Acceleration Exploration for Asip Architecture. IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, 20(4), p. 684-696. 
3Kowarzyk, G., Belanger, N., Haccoun, D., Savaria, Y. (2012). Efficient Search Algorithm for Determining Optimal R=1/2 Systematic Convolutional Self-Doubly Orthogonal Codes. IEEE Transactions on Communications, 60(1), p. 3-8. 
4Nourivand, A., Al-Khalili, A.J., Savaria, Y. (2012). Postsilicon Tuning of Standby Supply Voltage in Srams to Reduce Yield Losses Due to Parametric Data-Retention Failures. IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, 20(1), p. 29-41. 
5Singh, R., Audet, Y., Gagnon, Y., Savaria, Y., Boulais, E., Meunier, M. (2011). A Laser-Trimmed Rail-to-Rail Precision CMOS Operational Amplifier. IEEE Transactions on Circuits and Systems II: Express Briefs, 58(2), p. 75-79. 
6Farah, R., Gan, Q., Langlois, J.M.P., Bilodeau, G.-A., Savaria, Y. (2011). A Tracking Algorithm Suitable for Embedded Systems Implementation. 18th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2011, p. 256-259. 
7Tawk, M., Guchuan Zhu, Savaria, Y., Xue Liu, Jian Li, Fei Hu (2011). A Tight End-to-End Delay Bound and Scheduling Optimization of an Avionics AFDX Network. IEEE.
8Zarrabi, H., Al-Khalili, A.J., Savaria, Y. (2011). Activity Management in Battery-Powered Embedded Systems: A Case Study of ZigBee&Reg WSN. 18th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2011, p. 727-731. 
9Kowarzyk, G., Belanger, N., Savaria, Y. (2011). A GPGPU-Based Software Implementation of the PBDI Deinterlacing Algorithm. 18th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2011, p. 780-783. 
10Vakili, S., Gil, D.C., Langlois, J.M.P., Savaria, Y., Bois, G. (2011). Customized Embedded Processor Design for Global Photographic Tone Mapping. 18th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2011, p. 382-385. 
11Tawk, M., Zhu, G., Savaria, Y., Liu, X., Li, J., Hu, F. (2011). A Tight End-to-End Delay Bound and Scheduling Optimization of an Avionics AFDX Network. 30th Digital Avionics Systems Conference - Closing the Generation Gap: Increasing Capability for Flight Operations Among Legacy, Modern and Uninhabited Aircraft, DASC 2011, p. 7B31-7B310. 
12Valorge, O., Andre, W., Savaria, Y., Blaquieie, Y. (2011). Power Supply Analysis of a Large Area Integrated Circuit. IEEE 9th International New Circuits and Systems Conference, NEWCAS 2011, p. 398-401. 
13Mahvash Mohammadi, H., Savaria, Y., Langlois, P. (2011). Hybrid Video Deinterlacing Algorithm Exploiting Reverse Motion Estimation. IET Image Processing, 5(7), p. 611-618. 
14Gil, D.C., Farah, R., Langlois, J.M.P., Bilodeau, G.-A., Savaria, Y. (2011). Comparative Analysis of Contrast Enhancement Algorithms in Surveillance Imaging. IEEE International Symposium of Circuits and Systems, ISCAS 2011, p. 849-852. 
15Hasan, S.R., Belanger, N., Savaria, Y., Ahmad, M.O. (2011). All Digital Skew Tolerant Synchronous Interfacing Methods for High-Performance Point-to-Point Communications in Deep Sub-Micron SoCs. Integration, The VLSI Journal, 44(1), p. 22-38. 
16Zarrabi, H., Al-Khalili, A., Savaria, Y. (2011). Repeater Insertion in Power-Managed VLSI Systems. 21st Great Lakes Symposium on VLSI, GLSVLSI 2011, p. 395-398. 
17Nourivand, A., Al-Khalili, A.J., Savaria, Y. (2011). Analysis of Resistive Open Defects in Drowsy SRAM Cells. Journal of Electronic Testing: Theory and Applications (JETTA), 27(2), p. 203-213. 
18Al-Terkawi Hasib, O., Sawan, M., Savaria, Y. (2011). A Low-Power Asynchronous Step-Down DCDC Converter for Implantable Devices. IEEE Transactions on Biomedical Circuits and Systems, 5(3), p. 292-301. 
19Boulais, E., Fantoni, J., Chateauneuf, A., Savaria, Y., Meunier, M. (2011). Laser-Induced Resistance Fine Tuning of Integrated Polysilicon Thin-Film Resistors. IEEE Transactions on Electron Devices, 58(2), p. 572-575. 
20Hasan, S.R., Belanger, N., Savaria, Y., Ahmad, M.O. (2010). Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(8), p. 2020-2031. 
21Zarrabi, H., Al-Khalili, A.J., Savaria, Y. (2010). An Interconnect-Aware Dynamic Voltage Scaling Scheme for DSM VLSI. IEEE International Symposium on Circuits and Systems. ISCAS 2010, p. 41-44. 
22Hasib, O.A., Sawan, M., Savaria, Y. (2010). Fully Integrated Ultra-Low-Power Asynchronously Driven Step-Down DC-DC Converter. IEEE International Symposium on Circuits and Systems. ISCAS 2010, p. 877-880. 
23Marche, D., Savaria, Y. (2010). Modeling R-2R Segmented-Ladder DACs. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(1), p. 31-43. 
24Chebli, R., Sawan, M., El-Sankary, K., Savaria, Y. (2010). High-Voltage DMOS Integrated Circuits Using Floating-Gate Protection Technique. Analog Integrated Circuits and Signal Processing, 62(2), p. 223-235. 
25Berriah, O., Bougataya, M., Lakhssassi, A., Blaquiere, Y., Savaria, Y. (2010). Thermal Analysis of a Miniature Electronic Power Device Matched to a Silicon Wafer. 8th IEEE International NEWCAS Conference (NEWCAS 2010), p. 129-132. 
26Tanguay, L.-F., Savaria, Y., Sawan, M. (2010). A 640 W Frequency Synthesizer Dedicated to Implantable Medical Microsystems in 90-Nm CMOS. 8th IEEE International NEWCAS Conference (NEWCAS 2010), p. 369-372. 
27Hasan, S.R., Belanger, N., Savaria, Y., Ahmad, M.O. (2010). Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(10), p. 2696-707. 
28Naderi, A., Sawan, M., Savaria, Y. (2009). A Low-Power 2 GHz Data Conversion Using Delta Modulation for Portable Application. Integration, the VLSI Journal, 42(1), p. 68-76. 
29Hashemi, S., Sawan, M., Savaria, Y. (2009). A Novel Low-Drop CMOS Active Rectifier for RF-Powered Devices: Experimental Results. Microelectronics Journal, 40(11), p. 1547-1554. 
30Mahoney P., Savaria Y., Bois G., Plante P. (2009). Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories. Transactions on High-Performance Embedded Architectures and Compilers. II. Berlin, Germany: Springer Verlag. p. 307-325.
31Hashemi, S., Sawan, M., Savaria, Y. (2009). Fully-Integrated Low-Voltage High-Efficiency CMOS Rectifier for Wirelessly Powered Devices. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference.
32Zarrabi, H., Al-Khalili, A.J., Savaria, Y. (2009). An Interconnect-Aware Delay Model for Dynamic Voltage Scaling in Nm Technologies. 19th ACM Great Lakes Symposium on VLSI, p. 45-49. 
33Ayachi, D., Savaria, Y., Thibeault, C. (2009). A Configurable Platform for MPSoCs Based on Application Specific Instruction Set Processors. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference.
34Basile-Bellavance, Y., Blaquiere, Y., Savaria, Y. (2009). Faults Diagnosis Methodology for the WaferNet Interconnection Network. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference.
35Aubertin, P., Mohammadi, H.M., Savaria, Y., Langlois, J.M.P. (2009). High Performance ASIP Implementation of PBDI: a New Intra-Field Deinterlacing Method. Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference.
36Hasan, S.R., Pontikakis, B., Savaria, Y. (2009). An All-Digital Skew-Adaptive Clock Scheduling Algorithm for Heterogeneous Multiprocessor Systems on Chips (MPSoCs). IEEE International Symposium on Circuits and Systems, p. 2501-2504. 
37Lepercq, E., Blaquiere, Y., Norman, R., Savaria, Y. (2009). Workflow for an Electronic Configurable Prototyping System. IEEE International Symposium on Circuits and Systems, p. 2005-2008. 
38Marche, D., Savaria, Y., Gagnon, Y. (2009). An Improved Switch Compensation Technique for Inverted R-2R Ladder DACs. IEEE Transactions on Circuits and Systems I: Regular Papers, 56(6), p. 1115-1124. 
39Beucher, N., Belanger, N., Savaria, Y., Bois, G. (2009). High Acceleration for Video Processing Applications Using Specialized Instruction Set Based on Parallelism and Data Reuse. Journal of Signal Processing Systems, 56(2-3), p. 155-165. 
40Tanguay, L.-F., Sawan, M., Savaria, Y. (2009). A Very-High Output Impedance Charge Pump for Low-Voltage Low-Power PLLs. Microelectronics Journal, 40(6), p. 1026-1031. 
41Zarreabi, H., Al-Khalili, A.J., Savaria, Y. (2009). Estimation of Energy Performance in Computing Platforms. 16th IEEE International Conference on Electronics, Circuits and Systems, p. 783-786. 
42Hashemi, S., Sawan, M., Savaria, Y. (2009). A Low-Area Power-Efficient CMOS Active Rectifier for Wirelessly Powered Medical Devices. 16th IEEE International Conference on Electronics, Circuits and Systems, p. 635-638. 
43Bafumba-Lokilo, D., Savaria, Y., David, J.-P. (2009). Generic Array-Based MPSoC Architecture. 2nd Microsystems and Nanoelectronics Research Conference, p. 128-131. 
44Lepercq, E., Valorege, O., Basile-Bellavance, Y., Laflamme-Mayer, N., Blaquière, Y., Savaria, Y. (2009). An Interconnection Network for a Novel Reconfigurable Circuit Board. 2nd Microsystems and Nanoelectronics Research Conference, p. 128-131. 
45Naderi, A., Sawan, M., Savaria, Y. (2009). Undersampling Delta-Sigma Modulators : Theory, Design and Implementation. Lambert Academic Publishers. 
46Naderi, A., Sawan, M., Savaria, Y. (2008). On the Design of Undersampling Continuous-Time Bandpass Delta - Sigma Modulators for Gigahertz Frequency A/D Conversion. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(11), p. 3488-3499. 
47Valorge, O., Nguyen, A.T., Blaquière, Y., Norman, R., Savaria, Y. (2008). Digital Signal Propagation on a Wafer-Scale Smart Active Programmable Interconnect. 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, p. 1059-1062. 
48Tremblay, J.-P., Savaria, Y., Thibeault, C., Mbaye, M. (2008). Improving Resource Utilization in an Multiple Asynchronous ALU DSP Architecture. 1st Microsystems and Nanoelectronics Research Conference, p. 25-28. 
49Basile-Bellavance, Y., Lepercq, E., Blaquiere, Y., Savaria, Y. (2008). Hardware/Software System Co-Verification of an Active Reconfigurable Board With SystemC-VHDL. 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008), p. 1159-1162. 
50Hasan, S.R., Belanger, N., Savaria, Y. (2008). All-Digital Skew-Tolerant Interfacing Method for Systems With Rational Frequency Ratios Among Multiple Clock Domains: Leveraging a Priori Timing Information. 1st Microsystems and Nanoelectronics Research Conference, p. 129-132. 
51Boulais, E., Binet, V., Degorce, J.Y., Wild, G., Savaria, Y., Meunier, M. (2008). Thermodynamics and Transport Model of Charge Injection in Silicon Irradiated by a Pulsed Focused Laser. IEEE Transactions on Electron Devices, 55(10), p. 2728-2735. 
52Salomon, M.E., Izouggaghen, B., Khouas, A., Savaria, Y. (2008). Spur Model for a Fixed-Frequency Signal Subject to Periodic Jitter. IEEE Transactions on Instrumentation and Measurement, 57(10), p. 2320-2328. 
53Marche, D., Savaria, Y., Gagnon, Y. (2008). Laser Fine-Tuneable Deep-Submicrometer Cmos 14-Bit Dac. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(8), p. 2157-2165. 
54Sahraii, N., Savaria, Y., Thibeault, C., Gagnon, F. (2008). Scheduling of Turbo Decoding on a Multiprocessor Platform to Manage Its Processing Effort Variability. Joint International IEEE Northeast Workshop on Circuits and Systems (NEWCAS) and TAISA Conference (NEWCAS-TAISA), p. 73-76. 
55Norman, R., Valorge, O., Blaquiere, Y., Lepercq, E., Basile-Bellavance, Y., El-Alaoui, Y., Prytula, R., Savaria, Y. (2008). An Active Reconfigurable Circuit Board. 2008 Joint International IEEE Northeast Workshop on Circuits and Systems (NEWCAS) and TAISA Conference (NEWCAS-TAISA), p. 351-354. 
56Pontikakis, B., Bui, H.T., Boyer, F.-R., Savaria, Y. (2008). A Novel Phase-Locked Loop (PLL) Architecture Without an Analog Loop Filter for Better Integration in Ultra-Deep Submicron SoCs. Joint International IEEE Northeast Workshop on Circuits and Systems (NEWCAS) and TAISA Conference (NEWCAS-TAISA 2008), p. 363-366. 
57Bafumba-Lokilo, D., Savaria, Y., David, J.-P. (2008). Generic Crossbar Network on Chip for FPGA MPSoCs. 2008 Joint International IEEE Northeast Workshop on Circuits and Systems (NEWCAS) and TAISA Conference (NEWCAS-TAISA), p. 269-272. 
58Ngoyi, G.-A.B., Pierre Langlois, J.M., Savaria, Y. (2008). Iterative Design Method for Video Processors Based on an Architecture Design Language and Its Application to ELA Deinterlacing. 2008 Joint International IEEE Northeast Workshop on Circuits and Systems (NEWCAS) and TAISA Conference (NEWCAS-TAISA), p. 37-40. 
59Norman, R., Lepercq, E., Blaquiere, Y., Valorge, O., Basile-Bellavance, Y., Prytula, R., Savaria, Y. (2008). An Interconnection Network for a Novel Reconfigurable Circuit Board. 2008 Joint International IEEE Northeast Workshop on Circuits and Systems (NEWCAS) and TAISA Conference (NEWCAS-TAISA), p. 129-132. 
60Zhao Lu, El-Fouladi, J., Martel, S., Savaria, Y. (2008). A Hybrid Bacteria and Microparticle Detection Platform on a CMOS Chip: Design, Simulation and Testing Considerations. 2008 IEEE 14th International Mixed-Signals, Sensors, and Systems Test Workshop (IMS3TW 2008).
61Mbaye, M., Belanger, N., Savaria, Y., Pierre, S. (2008). Loop-Oriented Metrics for Exploring an Application-Specific Architecture Design-Space. International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2008), p. 257-262. 
62Kowarzyk, G., Savaria, Y., Haccoun, D. (2008). Searching for Short-Span Convolutional Doubly Self-Orthogonal Codes: a Parallel Implicitly-Exhaustive-Search Algorithm. Canadian Conference on Electrical and Computer Engineering - CCECE 2008, p. 001659-001662. 
63Bui, H.T., Savaria, Y. (2008). Design of a High-Speed Differential Frequency-to-Voltage Converter and Its Application in a 5-Ghz Frequency-Locked Loop. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(3), p. 766-774. 
64Nourivand, A., Al-Khalili, A.J., Savaria, Y. (2008). Aggressive Leakage Reduction of SRAMs Using Error Checking and Correcting (ECC) Techniques. IEEE International 51st Midwest Symposium on Circuits and Systems, MWSCAS, p. 426-429. 
65Bougataya, M., Lakhsasi, A., Norman, R., Prytula, R., Blaquière, Y., Savaria, Y. (2008). Steady State Thermal Analysis of a Reconfigurable Wafer-Scale Circuit Board. IEEE Canadian Conference on Electrical and Computer Engineering, CCECE 2008, May 04,2008 - May 07,2008, p. 411-415. 
66Anane, A., Aboulhamid, E.M., Vachon, J., Savaria, Y. (2008). Modeling and Simulation of Complex Heterogeneous Systems. IEEE International Symposium on Circuits and Systems, ISCAS 2008, p. 2873-2876. 
67Tanguay, L.F., Sawan, M., Savaria, Y. (2008). A Very-High Output Impedance Current Mirror for Very-Low Voltage Biomedical Analog Circuits. IEEE Asia-Pacific Conference on Circuits and Systems, p. 642-645. 
68Deca, R., Cherkaoui, O., Savaria, Y., Slone, D. (2007). Constraint-Based Model Service for Network Provisioning. Annales des télécommunications, 62(7-8), p. 847-870. 
69El Fouladi, J., Lu, Z., Savaria, Y., Martel, S. (2007). An Integrated Biosensor for the Detection of Bio-Entities Using Magnetotactic Bacteria and CMOS Technology.. EMBC'07. Proceedings of the 29th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, v. 2007 , p. 119-122. 
70Mohammadi, H.M., Langlois, P., Savaria, Y. (2007). A Five-Field Motion Compensated Deinterlacing Method Based on Vertical Motion. IEEE Transactions on Consumer Electronics, 53(3), p. 1117-1124. 
71Saheb, J.-F., Richard, J.-F., Sawan, M., Meingan, R., Savaria, Y. (2007). System Integration of High Voltage Electrostatic MEMS Actuators. Analog Integrated Circuits and Signal Processing, 53(1), p. 27-34. 
72Pontikakis, B., Bui, H.T., Boyer, F.-R., Savaria, Y. (2007). A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs. ISCAS 2007. Proceedings of the IEEE International Symposium on Circuits and Systems, p. 633-636. 
73Chebli, R., Sawan, M., Savaria, Y., El-Sankary, K. (2007). High-Voltage DMOS Integrated Circuits With Floating Gate Protection Technique. 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007,, p. 3343-3346. 
74Singh, R., Audet, Y., Gagnon, Y., Savaria, Y. (2007). Integrated Circuit Trimming Technique for Offset Reduction in a Precision CMOS Amplifier. ISCAS 2007. Proceedings of the IEEE International Symposium on Circuits and Systems, p. 709-712. 
75Binet, V., Savaria, Y., Meunier, M., Gagnon, Y. (2007). Modeling the Substrate Noise Injected by a DC-DC Converter. ISCAS 2007. Proceedings of the IEEE International Symposium on Circuits and Systems, p. 309-312. 
76Gorse, N., Belanger, P., Chureau, A., Aboulhamid, E.M., Savaria, Y. (2007). A High-Level Requirements Engineering Methodology for Electronic System-Level Design. Computers & Electrical Engineering, 33(4), p. 249-268. 
77Mbaye, M.M., Belanger, N., Savaria, Y., Pierre, S. (2007). A Novel Application-Specific Instruction-Set Processor Design Approach for Video Processing Acceleration. Journal of VlSI Signal Processing Systems for Signal Image and Video Technology, 47(3), p. 297-315. 
78Lu, Z., El-Fouladi, J., Savaria, Y., Martel, S. (2007). A Hybrid Bacteria and Microparticle Detection Platform on a CMOS Chip. 11th International Conference on Miniaturized Systems for Chemistry and Life Science.
79Hashemi, S., Sawan, M., Savaria, Y. (2007). A Novel Fully-Integrated Low-Drop Voltage Cmos Rectifier for Wirelessly Powered Devices. IEEE International Conference on Microelectronics.
80Valorge, O., Marche, D., Lacourse, A., Sawan, M., Savaria, Y. (2007). Signal Integrity Analysis of a High Precision D/A Converter. 14th IEEE International Conference on Electronics, Circuits and Systems, p. 1224-1227. 
81Abderrahman, A., Savaria, Y., Khouas, A., Sawan, M. (2007). New Analog Test Metrics Based on Probabilistic and Deterministic Combination Approaches. 14th IEEE International Conference on Electronics, Circuits and Systems, p. 82-85. 
82Abderrahman, A., Savaria, Y., Khouas, A., Sawan, M. (2007). Accurate Testability Analysis Based-on Multi-Frequency Test Generation and a New Testability Metric. IEEE Northeast Workshop on Circuits and Systems. NEWCAS 2007, p. 1356-1359. 
83Naderi, A., Sawan, M., Savaria, Y. (2007). A 1.8GHz CMOS Continuous-Time Band-Pass Delta-Sigma Modulator for RF Receivers. 50th Midwest Symposium on Circuits and Systems. MWSCAS 2007, p. 1078-1081. 
84Trabelsi, A., Boyer, F.R., Savaria, Y. (2007). Speech Enhancement Based Noise PSD Estimator to Remove Cosine Shaped Residual Noise. 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS '07), p. 393-396. 
85Pontikakis, B., Boyer, F.-R., Savaria, Y., Bui, H.T. (2007). Precise Free-Running Period Synthesizer (FRPS) With Process and Temperature Compensation. 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS '07), p. 1118-1121. 
86Trabelisi, A., Boyer, F.R., Savaria, Y., Boukadoum, M. (2007). Iterative Noise-Compensated Method to Improve LPC Based Speech Analysis. 14h IEEE International Conference on Electronics, Circuits & Systems, p. 1364-1367. 
87Trabelisi, A., Boyer, F.R., Savaria, Y., Boukadoum, M. (2007). Improving LPC Analysis of Speech in Additive Noise. IEEE Northeast Workshop on Circuits and Systems. NEWCAS 2007, p. 93-96. 
88Deslauriers, F., Langevin, M., Bois, G., Savaria, Y., Paulin, P. (2006). RoC: a Scalable Network on Chip Based on the Token Ring Concept. The 4th International IEEE-NEWCAS Conference.
89Chureau, A., Savaria, Y., Boland, J.-F., Zilic, Z., Thibeault, C., Gagnon, F. (2006). Building Heterogeneous Functional Prototypes Using Articulated Interfaces. The 4th International IEEE-NEWCAS Conference.
90Bui, H.T., Savaria, Y. (2006). High Speed Differential Pulse-Width Control Loop Based on Frequency-to-Voltage Converters. GLSVLSO '06 : Proceedings of the 16th ACM Great Lakes Symposium on VLSI.
91Belanger, N., Savaria, Y. (2006). On the Design of a Double Precision Logarithmic Number System Arithmetic Unit. The 4th International IEEE-NEWCAS Conference.
92Nicolescu, B., Ignat, N., Savaria, Y., Nicolescu, G. (2006). Analysis of Real-Time Systems Sensitivity to Transient Faults Using MicroC Kernel. IEEE Transactions on Nuclear Science, 53(4), p. 1902-1909. 
93Naderi, A., Sawan, M., Savaria, Y. (2006). A Novel 2-GHz Band-Pass Delta Modulator Dedicated to Wireless Receivers. 2006 IEEE International Symposium on Circuits and Systems.
94Pontikakis, B., Boyer, F.-R., Savaria, Y. (2006). A 0.8V Algorithmically Defined Buffer and Ring Oscillator Low-Energy Design for Nanometer SoCs. 2006 IEEE International Symposium on Circuits and Systems, p. 1259-1262. 
95Mbaye, M., Lebel, D., Belanger, N., Savaria, Y., Pierre, S. (2006). Design Exploration With an Application-Specific Instruction-Set Processor for ELA Deinterlacing. 2006 IEEE International Symposium on Circuits and Systems.
96Huang, Z., Savaria, Y., Sawan, M., Meinga, R. (2006). High-Voltage Operational Amplifier Based on Dual Floating-Gate Transistors. 2006 IEEE International Symposium on Circuits and Systems.
97Cantin, M.-A., Savaria, Y., Prodanos, D., Lavoie, P. (2006). A Metric for Automatic Word-Length Determination of Hardware Datapaths. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 25(10), p. 2228-31. 
98Castonguay, A., Savaria, Y. (2006). Architecture of a Hypertransport Tunnel. 2006 IEEE International Symposium on Circuits and Systems.
99Hashemi, S., Sawan, M., Savaria, Y. (2006). A Power Planning Model for Implantable Stimulators. 2006 IEEE International Symposium on Circuits and Systems.
100Boyer, F.R., Epassa, H.G., Savaria, Y. (2006). Embedded Power-Aware Cycle by Cycle Variable Speed Processor. IEE Proceedings-Computers and Digital Techniques, 153(4), p. 283-290. 
101Dubois, M., Savaria, Y., Haccoun, D., Belanger, N. (2006). Low-Power Configurable and Generic Shift Register Hardware Realisations for Convolutional Encoders and Decoders. IEE Proceedings. Circuits, Devices and Systems, 153(3), p. 207-213. 
102Ignat, N., Nicolescu, B., Savaria, Y., Nicolescu, G. (2006). Soft-Error Classification and Impact Analysis on Real-Time Operating Systems. 2006 Design Automation and Test in Europe. Proceedings, p. 180-185. 
103Mahvash Mohammadi, H., Langlois, J.M.P., Savaria, Y. (2006). A Threshold-Based De-Interlacing Algorithm Using Motion Compension and Directional Interpolation. Proceedings of the IEEE International Conference on Electronics, Circuits and Systems.
104Mahvash, M.H., Savaria, Y., Langlois, J.M.P. (2006). Real-Time ELA De-Interlacing With the Xtensa Reconfigurable Processor. The 4th International IEEE-NEWCAS Conference, p. 25-28. 
105El fouladi, J., André, W., Savaria, Y., Martel, S. (2006). System Design of an Integrated Measurement Electronic Subsystem for Bacteria Detection Using and Electrode Array and MC-1 Magnetotactic Bacteria. International Workshop on Computer Architecture for Machine Perception and Sensing, p. 38-41. 
106Naderi, A., Sawan, M., Savaria, Y. (2006). Design of an Active-RC Bandpass Filter for a Subsampling RF Delta Modulator. CCECE'06 Canadian Conference on Electrical and Computer Engineering, p. 967-970. 
107Mohammadi, H.M., Langlois, J.M.P., Savaria, Y. (2006). A Threshold-Based Deinterlacing Algorithm Using Motion Compensation and Directional Interpolation. 13th IEEE International Conference on Electronics, Circuits and Systems, p. 459-462. 
108Nicolescu, B., Gorse, N., Savaria, Y., Aboulhamid, E.M., Velazco, R. (2005). On the Use of Model Checking for the Verification of a Dynamic Signature Monitoring Approach. IEEE Transactions on Nuclear Science, 52(5), p. 1555-1561. 
109Sawan, M., Djemouai, A., El-Sankary, K., Dang, H., Naderi, A., Savaria, Y., Gagnon, F. (2005). High Speed ADCs Dedicated for Wideband Wireless Receivers. The 3rd International IEEE-NEWCAS Conference, p. 283-286. 
110Morin, D., Savaria, Y., Sawan, M. (2005). A 200 MSPS 10-Bit Pipelined ADC Using Digital Calibration. The 3rd International IEEE-NEWCAS Conference,, p. 67-70. 
111Naderi, A.H., Sawan, M., Savaria, Y. (2005). A 1-MW 2-GHz Q-Enhanced LC Bandpass Filter for Low-Power RF Applications. The 3rd International IEEE-NEWCAS Conference, p. 365-368. 
112Bui, H.T., Savaria, Y. (2005). High-Speed Differential Frequency-to-Voltage Converter. The 3rd International IEEE-NEWCAS Conference, p. 373-376. 
113Mahoney, P., Savaria, Y., Bois, G., Plante, P. (2005). Parallel Hashing Memories : an Alternative to Content Addressable Memories. The 3rd International IEEE-NEWCAS Conference, p. 223-226. 
114Chabini, N., Aboulhamid, E.M., Chabini, I., Savaria, Y. (2005). Scheduling and Optimal Register Placement for Synchronous Circuits Derived Using Software Pipelining Techniques. Acm Transactions on Design Automation of Electronic Systems, 10(2), p. 187-204. 
115Grou-Szabo, R., Ghattas, H., Savaria, Y., Nicolescu, G. (2005). Component-Based Methodology for Hardware Design of a Dataflow Processing Network. Fifth International Workshop on System-on-Chip for Real-Time Applications, Proceedings, p. 289-294. 
116Pontikakis, B., Boyer, F.R., Savaria, Y. (2005). Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period. Fifth International Workshop on System-on-Chip for Real-Time Applications, Proceedings, p. 454-458. 
117Bui, H.T., Savaria, Y. (2005). A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in Socs. Fifth International Workshop on System-on-Chip for Real-Time Applications, Proceedings, p. 557-562. 
118Marche, D., Savaria, Y., Gagnon, Y. (2005). A New Switch Compensation Technique for Inverted R-2r Ladder Dacs. 2005 IEEE International Symposium on Circuits and Systems (Iscas), Conference Proceedings, v. 1, p. 196-199. 
119Epassa, H.G., Boyer, F.R., Savaria, Y. (2005). Implementation of a Cycle by Cycle Variable Speed Processor. 2005 IEEE International Symposium on Circuits and Systems (Iscas), Conference Proceedings, v. 4, p. 3335-3338. 
120Catudal, S., Cantin, M.A., Savaria, Y. (2005). Parameters Estimation Applied to Automatic Video Processing Algorithms Validation. 2005 IEEE International Symposium on Circuits and Systems (Iscas), Conference Proceedings, v. 4, p. 3439-3442. 
121Mbaye, M., Bélanger, N., Savaria, Y., Pierre, S. (2005). Application Specific Instruction-Set Processor Generation for Video Processing Based on Loop Optimization. 2005 IEEE International Symposium on Circuits and Systems (Iscas), Conference Proceedings, v. 4, p. 3515-3518. 
122Wild, G., Savaria, Y., Meunier, M. (2005). Characterization of Laser-Induced Photoexcitation Effect on a Surrounding CMOS Ring Oscillator. 2005 IEEE International Symposium on Circuits and Systems (Iscas), Conference Proceedings, v. 4, p. 3696-3699. 
123Salomon, M.E., Khouas, A., Savaria, Y. (2005). A Complete Spurs Distribution Model for Direct Digital Period Synthesizers. 2005 IEEE International Symposium on Circuits and Systems (Iscas), Conference Proceedings, v. 5, p. 4859-4862. 
124Dang, H., Sawan, M., Savaria, Y. (2005). A Novel Approach for Implementing Ultra-High Speed Flash Adc Using Mcml Circuits. 2005 IEEE International Symposium on Circuits and Systems (Iscas), Conference Proceedings, v. 6, p. 6158-6161. 
125Castonguay, A., Savaria, Y. (2005). A Hypertransport Chip-to-Chip Interconnect Tunnel Developed Using Systemc. 16th International Workshop on Rapid System Prototyping, Proceedings. Shortening the Path From Specification to Prototype, p. 264-266. 
126Dubois, M., Savaria, Y., Bois, G. (2005). A Generic Ahb Bus for Implementing High-Speed Locally Synchronous Islands. Proceedings of the IEEE SoutheastCon 2004 : Excellence in Engineering, Science, and Technology, p. 11-16. 
127Ling, W., Savaria, Y. (2005). Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations. 6th International Symposium on Quality Electronic Design, Proceedings, p. 688-693. 
128Chureau, A., Savaria, Y., Aboulhamid, E.M. (2005). The Role of Model-Level Transactors and Uml in Functional Prototyping of Systems-on-Chip: a Software-Radio Application. Design, Automation and Test in Europe. Conference and Exhibition, Proceedings, p. 698-703. 
129Khali, H., Savaria, Y., Houle, J.-L. (2005). A System Level Implementation Strategy and Partitioning Algorithm for Applications Based on Lookup Tables. International Journal of Computer and Electrical Engineering, 31(7), p. 485-502. 
130Dubois, M., Savaria, Y., Haccoun, D., Bélanger, N. (2005). On Low Power Configurable and Generic Shift Register Hardware Realizations for Convolutional Encoders and Decoders. IEE Proceedings. Circuits, Devices and Systems. 
131Chebli, R., Sawan, M., Savaria, Y. (2005). Gate Oxide Protection in HV CMOS/DMOS Integrated Circuits: Design and Experimental Results. IEEE-ICECS.
132Nicolescu, B., Ignat, N., Savaria, Y., Nicolescu, G. (2005). Sensitivity of Real-Time Operating Systems to Transient Faults : A Cause Study for MicroC Kernel. 8th European Conference on Radiation and Its Effects on Components and Systems (RADECS 2005).
133Deca, R., Mahrez, O., Cherkaoui, O., Savaria, Y., Slone, D. (2005). Contributions to Automated Testing of Network Service Interactions. 5e Colloque International sur les nouvelles technologies de la répartition, p. 175-180. 
134Chebli, R., Sawan, M., Savaria, Y. (2005). A Programmable Posititve and Negative High-Voltage DC-DC Converter Dedicated for Ultrasonic Applications. IEEE-MWSCAS, p. 679-682. 
135Bui, H.T., Savaria, Y. (2005). Design and Analysis of XOR Gates for High-Speed and Low-Jitter Applications. 9th World Multi-Conference on Systemics, Cybernetics and Informatics (WMSCI 2005), p. 60-65. 
136Landry, A., Savaria, Y., Nekili, M. (2005). Circuits Techniques for a 2 GHz AMBA AHB Bus. NEWCAS 2005, p. 311-314. 
137Saheb, J.F., Richard, J.-F., Meingan, R., Sawan, M., Savaria, Y. (2005). System Integration of High Voltage Electrostatic MEMS Actuators. NEWCAS 2005, p. 155-158. 
138Landry, A., Nekili, M., Savaria, Y. (2005). A Novel 2 GHz Mulit-Layer AMBA High-Speed Bus Interconnect Matrix for SoC Platforms. ISCAS 2005, p. 3343-3346. 
139Provost, G., Cantin, M.A., Sawan, M., Cardinal C., Savaria, Y., Haccoun, D. (2005). Fast Parameters Optimization of an Iterative Decoder Using a Configurable Hardware Accelerator. IEEE-ISCAS 2005, v. 4, p. 4159-4162. 
140Rioux, S., Lacourse, A., Ducharme, M., Gagnon, Y., Savaria, Y., Meunier, M. (2005). Design Methods for CMOS Low-Current Finely Tunable Voltage References Covering a Wide Output Range. ISCAS 2005, p. 4257-4260. 
141Hashemi, S., Sawan, M., Savaria, Y. (2005). Modeling Power Budget Requirements of Implantable Electronic Devices. IEEE-ICECS.
142Boland, J.F., Chureau, A., Thibeault, C., Savaria, Y., Gagnon, F., Zilic, Z. (2004). An Efficient Methodology for Design and Verification of an Equalizer for a Software Defined Radio. NEWCAS 2004, p. 73-76. 
143Boudjella, A., Jin, Z.F., Savaria, Y. (2004). Electrical Field Analysis of Nanoscale Field Effect Transistors. Japanese Journal of Applied Physics Part 1-Regular Papers Short Notes & Review Papers, 43(6), p. 3831-3837. 
144Bougataya, M., Lakhasasi, A., Savaria, Y., Massicotte, D. (2004). Thermo-Mechanical Stress Analysis of VLSI Devices by Partially Coupled Finite Element Method. 18th Annual Canadian Conference on Electrical and Computer Engineering CCEC04, v. 1, p. 509-513. 
145Boyer, F.-R., Epassa, H.G., Pontikakis, B., Savaria, Y., Ling, W. (2004). A Variable Period Clock Synthesis (VPCS) Architecture for Next-Generation Power-Aware SoC Applications. NEWCAS 2004, p. 145-148. 
146Bui, T., Savaria, Y. (2004). Shunt-Peaking of MCML Gates Using Active Inductors. NEWCAS 2004, p. 361-364. 
147Calbaza, D.E., Cordos, I., Seth-Smith, N., Savaria, Y. (2004). An Adpll Circuit Using a Ddps for Genlock Applications. 2004 IEEE International Symposium on Circuits and Systems, v. 4, p. 569-572. 
148Cantin, M.A., Savaria, Y., Velazco, R. (2004). An Automatic Word Length Determination Method. WSEAS Transaction on Information Science & Applications, 1(5), p. 1440-1448. 
149Catudal, S., Cantin, M.-A., Savaria, Y. (2004). Performance Driven Validation Applied to Video Processing. WSEAS Transactions on Electronics, 1(3), p. 568-575. 
150Chureau, A., Savaria, Y., Aboulhamid, E.M. (2004). Interface-Based Design of Systems-on-Chip Using UML-RT. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, p. 39-44. 
151Dubois, M., Bois, G., Savaria, Y. (2004). Double Profiling Methodology for Video Processing Platform. WSEAS Transactions on Computers, 3(6), p. 1802-1807. 
152Dubois, M., Savaria, Y., Haccoun, D. (2004). On Low Power Shift Register Hardware Realizations for Convolutional Encoders and Decoders. Conference Proceedings - 2nd Annual IEEE Northeast Workshop on Circuits and Systems, NEWCAS 2004, p. 213-216. 
153Duval, O., Lafrance, L.P., Savaria, Y., Desjardins, R. (2004). An Integrated Test Platform for Nanostructure Electrical Characterization. 2004 International Conference on Mems, Nano and Smart Systems, Proceedings, p. 237-242. 
154Duval, O., Savaria, Y. (2004). An on-Chip Delay Measurements Module for Nanostructures Characterization. 2004 IEEE International Symposium on Circuits and Systems, v. 3, p. 721-724. 
155Gorse, N., Aboulhamid, E.M., Savaria, Y. (2004). Consistency Validation of High-Level Requirements. IWSOC 2004, p. 93-98. 
156Gorse, N., Bélanger, P., Aboulhamid, E.M., Savaria, Y. (2004). Mixing Linguistic and Formal Techniques for High-Level Requirements Engineering. ICM 2004 : the 16th International Conference on Microelectronics, Proceedings, p. 339-342. 
157Gorse, N., Metzger, M., Lapalme, J., Aboulhamid, E.M., Savaria, y., Nicolescu, G. (2004). Enhancing ESys.Net With a Semi-Formal Verification Layer. ICM 2004 : the 16th International Conference on Microelectronics, Proceedings, p. 388-391. 
158Granger, E., Catudal, S., Grou, R., Mbaye, M.M., Savaria, Y. (2004). On Current Strategies for Hardware Acceleration of Digital Image Restoration Filters. 4th WSEAS Int. Conf. on Signal, Speech and Image Processing (ICOSSIP 2004).
159Hasan, S.R., Landry, A., Savaria, Y., Nekili, M. (2004). Design Constraints of Hypertransport-Compatible Networks-on-Chip. NEWCAS 2004, p. 269-272. 
160Hashemi, S., Sawan, M., Savaria, Y. (2004). Characterization of Stress Induced Defects in Deep Sub-Micron MOSFETS. Conference Proceedings - 2nd Annual IEEE Northeast Workshop on Circuits and Systems, NEWCAS 2004, p. 329-332. 
161Huang, Z., Savaria, Y., Sawan, M. (2004). Robust Design of a Dynamically Controlled Low-Power Level-Up Shifter Operating Up to 300V. NEWCAS 2004, p. 321-324. 
162Bui, H.T., Savaria, Y. (2004). 10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 Mu m CMOS. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, p. 115-118. 
163Bui, H.T., Savaria, Y. (2004). Shunt-Peaking in MCML Gates and Its Application in the Design of a 20 Gb/s Half-Rate Phase Detector. 2004 IEEE International Symposium on Circuits and Systems, v. 4, p. 369-372. 
164Izouggaghen, B., Khouas, A., Savaria, Y. (2004). Spurs Modeling in Direct Digital Period Synthesizers Related to Phase Accumulator Truncation. 2004 IEEE International Symposium on Circuits and Systems, v. 3, p. 389-392. 
165Jiang, Y.T., Wang, Y.K., Song, X.Y., Savaria, Y. (2004). Computation of Signal Output Probability for Boolean Functions Represented by Obdd. Computers & Mathematics With Applications, 47(12), p. 1865-1874. 
166Lafrance, L.-P., Savaria, Y. (2004). A Framework for Implementing Reusable Digital Signal Processing Modules. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, p. 51-4. 
167Landry, A., Savaria, Y., Nekili, M. (2004). A Beyond-1 GHz High-Speed Bus for SoC DSP Platforms. ICM 2004 : the 16th International Conference on Microelectronics, Proceedings, p. 46-49. 
168Layachi, M., Savaria, Y., Rochefort, A. (2004). The Effect of Pi-Coupling on the Electronic Properties of 1,4-Dithiol Benzene Stacking. 2004 International Conference on Mems, Nano and Smart Systems, Proceedings, p. 588-592. 
169Ling, W., Savaria, Y. (2004). Variable-Precision Multiplier for Equalizer With Adaptive Modulation. MWSCAS 2004 : the 2004 47th Midwest Symposium on Circuits and Systems. Conference Proceedings, v. 1, p. 553-556. 
170Morin, D., Normandin, F., Grandmaison, M.E., Dang, H., Savaria, Y., Sawan, M. (2004). An Intellectual Property Module for Auto-Calibration of Time-Interleaved Pipelined Analog-to-Digital Converters. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, p. 111-114. 
171Nicolescu, B., Gorse, N., Savaria, Y., Aboulhamid, E.M., Velazco, R. (2004). Validating a Dynamic Signature Monitoring Approach Using the LTL Mocel Checking Technique. Workshop on Radiation Effects on Components and Systems RADECS 2004, p. 93-96. 
172Nicolescu, B., Savaria, Y., Velazco, R. (2004). Performance Evaluation and Failure Rate Prediction for the Soft Implemented Error Detection Technique. Proceedings. 10th IEEE International On-Line Testing Symposium, p. 233-238. 
173Nicolescu, B., Savaria, Y., Velazco, R. (2004). Software Detection Mechanisms Providing Full Coverage Against Single Bit-Flip Faults. IEEE Transactions on Nuclear Science, 51(6), p. 3510-3518. 
174Nsame, P., Savaria, Y. (2004). A Customizable Embedded SoC Platform Architecture. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, p. 299-304. 
175Nsame, P., Savaria, Y. (2004). Multi-Processor SoC Integration: a Case Study on BlueGene. SOCC 2004, p. 201-204. 
176Peterson, K., Savaria, Y. (2004). Assertion-Based on-Line Verification and Debug Environment for Complex Hardware Systems. 2004 IEEE International Symposium on Circuits and Systems, v. 2, p. 685-688. 
177Regimbal, S., Savaria, Y., Bois, G. (2004). Verification Strategy Determination Using Dependence Analysis of Transaction-Level Models. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, p. 87-92. 
178Richard, J.-F., Savaria, Y. (2004). High Voltage Charge Pump Using Standard CMOS Technology. NEWCAS 2004, p. 317-320. 
179Robert, M., Savaria, Y., Wang, C. (2004). Analysis of Metrics Used to Compare Analog-to-Digital Converters. NEWCAS 2004, p. 301-304. 
180Tanguay, B., Savaria, Y., Sawan, M. (2004). Accelerating Equalization Algorithms Using the Xtensa Configurable Processor. ICM 2004 : the 16th International Conference on Microelectronics, Proceedings, p. 434-437. 
181Tohio, B., Pierre, S., Savaria, Y., Mbaye, M.M. (2004). Algorithm and Criteria to Assess Protocol Convertibility in Network Processing Environments. WSEAS International Conference on Telecommunications and Informatics (TELE-INFO'04).
182Tohio, B., Pierre, S., Savaria, Y., Mbaye, m.M.M. (2004). Protocol Convertibility in Network Processing Environments. 6th WSEAS International Conference on Telecommunications and Informatics (TELE-INFO'04), v. 3, p. 1. 
183Zhengrong, H., Savaria, Y., Sawan, M. (2004). A Dynamically Controlled and Refreshed Low-Power Level-Up Shifter. MWSCAS-2004 : Conference Proceedings, v. 1, p. 97-100. 
184Zhong-Fang Jin, Minying Yang, Savaria, Y., Wu, K. (2004). Analysis of Gate Modulation in Nanoscale Field Effect Transistors Using an Equivalent Substrate Integrated Waveguide (SIW) Model. ANTEM 2004, p. 63-65. 
185Cantin, M.A., Regimbal, S., Catudal, S., Savaria, Y. (2004). A Unified Environment to Assess Image Quality in Video Processing. Journal of Circuits Systems and Computers, 13(6), p. 1289-1306. 
186Beaudin, S., Marceau, R.J., Bois, G., Savaria, Y., Kandil, N. (2003). An Economic Parallel Processing Technology for Faster Than Real-Time Transient Stability Simulation. European Transactions on Electrical Power, 13(2), p. 105-112. 
187Bissou, J.P., Savaria, Y. (2003). Conception de haut niveau d'une plate-forme SOC pour la conversion de protocoles réseaux. CCGEI'2003, v. 2, p. 1271-1274. 
188Boudjella, A., Jin, Z.F., Savaria, Y. (2003). Electrical Field Analysis of Nanoscaled Field Effect Transistors. International Microprocesses and Nanotechnology Conference, p. 240-241. 
189Bougataya, M., Lakhsasi, A., Savaria, Y., Massicotte, D. (2003). Stress and Distortion Behavior for VLSI Steady State Thermal Analysis. CCGEI'2003, v. 1, p. 111-116. 
190Catudal, S., Cantin, M.A., Savaria, Y. (2003). Performance Driven Validation Applied to Viseo Processing. WSEAS Transactions on Electronics, 1(3), p. 568-574. 
191Chabini, N., Chabini, I., Aboulhamid, E.M., Savaria, Y. (2003). Unification of Basic Retiming and Supply Voltage Scaling to Minimize Dynamic Power Consumption for Synchronous Digital Designs. GLSVLSI (Proceedings of the Great Leakes Symposium on VLSI), p. 221-224. 
192Chabini, N., Chabini, I., Aboulhamid, E.M., Savaria, Y. (2003). Methods for Minimizing Dynamic Power Consumption in Synchronous Designs With Multiple Supply Voltages. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(3), p. 346-351. 
193Ghattas, H., Mbaye, M.M., Pepga, J.B., Savaria, Y. (2003). SoC Platform Architecture for a Network Processor. International Symposium on System-on-Chip, p. 49-52. 
194Ghattas, H., Savaria, Y. (2003). Design of Dedicated Low Complexity Embedded Processors for SOC Network Processing Applications. 1st Northeast Workshop on Circuits and Systems NEWCAS'2003, p. 21-24. 
195Granger, E., Catudal, S., Grou, R., Mbaye, M.M., Savaria, Y. (2003). On Current Strategies for Hardware Acceleration of Digital Image Restoration Filters. WSEAS Transactions on Electronics, 1(3), p. 551-557. 
196Granger, E., Savaria, Y., Lavoie, P. (2003). A Pattern Reordering Approach Based on Ambiguity Detection for Online Category Learning. IEEE Transactions on Pattern Analysis and Machine Intelligence, 25(4), p. 524-528. 
197Jin, Z.F., Laurin, J.J., Savaria, Y. (2003). Comparison of Propagation Characteristics Between Single and Coupled Mis Interconnect Topologies in Vlsi Circuits. CCECE 2003 Canadian Conference on Electrical and Computer Engineering, Vols 1-3, Proceedings - Toward a Caring and Humane Technology, p. 5-8. 
198Khali, H., Savaria, Y. (2003). Hard-Ware Software Co Design Model for Real-Time 3D Image Computation Using Active Laser Range Finders: a Case Study. 10th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2003.
199Khali, H., Savaria, Y., Houle, J.L., Rioux, M., Beraldin, J.A., Poussart, D. (2003). Improvement of Sensor Accuracy in the Case of a Variable Surface Reflectance Gradient for Active Laser Range Finders. IEEE Transactions on Instrumentation and Measurement, 52(6), p. 1799-1808. 
200Lamarche, P.H., Savaria, Y. (2003). VHDL Source Code Generator and Analysis Tool to Design Linear Interpolars. 1st Northeast Workshop on Circuits and Systems NEWCAS'2003, p. 69-72. 
201Lemire, J.F., Aboulhamid, E.M., Savaria, Y., Bois, G., Baron, A. (2003). Implementing e Assertion Checkers From an SDL Executable Specifications. DVCON.
202Loiseau L., Savaria Y. (2003). Design Reuse. System-on-Chip for Real-Time Applications. Luwer academic publishers. p. 29-82.
203Loiseau, L., Savaria, Y. (2003). Methodologies and Strategies for Effective Design-Reuse. System-on-Chip for Real-Time Applications, p. 31-40. 
204Lu, M., Savaria, Y., Qiu, B., Taillefer, J. (2003). IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Water Safe Integration. DFT'03, p. 18-25. 
205Mbaye, M.M., Tohio, B., Savaria, Y., Pierre, S. (2003). Performance of a Firewire-Ethernet Protocols Conversion on an Arm7 Embedded Processor. CCECE 2003: Canadian Conference on Electrical and Computer Engineering, Vols 1-3, Proceedings - Toward a Caring and Humane Technology, p. 1267-1270. 
206Nicolescu, B., Perronnard, P., Velazco, R., Savaria, Y. (2003). Efficiency of Transient Bit-Flips Detection by Software Means a Complete Study. 18th Conference International Symposium in Defect and Fault Tolerant in VLSI Systems, p. 377-384. 
207Nicolescu, B., Savaria, Y., Velazco, R. (2003). SIED: Software Implemented Error Detection. Proceedings. 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, p. 589-596. 
208Nsame, P., Savaria, Y. (2003). System-Level Design Closure. 1st Northeast Workshop on Circuits and Systems NEWCAS'2003, p. 101-104. 
209Pepga bissou, J., Dubois, M., Savaria, Y., Bois, G. (2003). High Speed System Bus for a SoC Network Processing Platform. ICM'2003, p. 194-197. 
210Regimbal, S., Lemire, J.-F., Savaria, Y., Bois, G., Aboulhamid, E.M., Baron, A. (2003). Automating Functional Coverage Analysis Based on an Executable Specification. Proceedings the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, p. 228-234. 
211Regimbal, S., Lemire, J.F., Savaria, Y., Bois, G., Aboulhamid, M., Baron, A. (2003). Aspect Partitioning for Hardware Verification Reuse. System-on-Chip for Real-Time Applications, p. 51-60. 
212Renaud, M., Savaria, Y. (2003). A CMOS Three-State Frequency Detector Complementary to an Enhanced Linear Phase Detector for PLL, DLL or High Frequency Clock Skew Measurement. ISCAS 2003. International Symposium on Circuits and Systems, v. 3, p. 148-151. 
213Richard, J.F., Lessard, B., Meingan, R., Martel, S., Savaria, Y. (2003). High Voltage Interfaces for CMOS/DMOS Technologies. 1st Northeast Workshop on Circuits and Systems NEWCAS'2003, p. 93-96. 
214Tang, Y., Qian, L., Wang, Y., Savaria, Y. (2003). New Memory Reference Reduction Method for FFT Implementation on DSP. ISCAS 2003. International Symposium on Circuits and Systems, p. 111-116. 
215Tohio, B., Pierre, S., Savaria, Y., Mbaye, M.M. (2003). Protocol Convertibility in a Network Processing Environment. CCECE 2003 Canadian Conference on Electrical and Computer Engineering: Toward a Caring and Humane Technology, v. 2, p. 801-804. 
216Trabelsi, A., Savaria, Y., Audet, Y. (2003). Automatic Offset Correction Technique Based on Active Load Tuning. 1st Northeast Workshop on Circuits and Systems NEWCAS'2003, p. 5-8. 
217Bendali, A., Savaria, Y. (2002). Low-Voltage Bandgap Reference With Temperature Compensation Based on a Threshold Voltage Technique. 2002 IEEE International Symposium on Circuits and Systems, v. 3, p. 201-204. 
218Calbaza, D.E., Savaria, Y. (2002). A Direct Digital Period Synthesis Circuit. IEEE Journal of Solid-State Circuits, 37(8), p. 1039-1045. 
219Cantin, M.-A., Savaria, Y., Lavoie, P. (2002). A Comparison of Automatic Word Length Optimization Procedures. 2002 IEEE International Symposium on Circuits and Systems, v. 2, p. 612-615. 
220Chabini, N., Aboulhamid, E.M., Chabini, I., Savaria, Y. (2002). Minimizing the Number of Phases in Clocked Digital Designs Derived Using Modulo Scheduling Techniques. Icm 2002: 14th International Conference on Microelectronics, p. 92-95. 
221Dido, J., Geraudie, N., Loiseau, L., Payeur, O., Savaria, Y., Poirier, D. (2002). A Flexible Floating-Point Format for Optimizing Data-Paths and Operators in FPGA Based DSPs. FPGA 2002: Tenth ACM International Symposium on Field-Programmable Gate Arrays, p. 50-55. 
222Fouzar, Y., Savaria, Y., Sawan, M. (2002). A CMOS Phase-Locked Loop With an Auto-Calibrated VCO. 2002 IEEE International Symposium on Circuits and Systems, v. 3, p. 177-180. 
223Hashemi, S., Sawan, M., Savaria, Y. (2002). Analysis of Power Chains in Transcutaneously Powered Electronic Implants. IFESS, p. 196-198. 
224Lafrance, L.-P., Cantin, M.-A., Savaria, Y., Sung, S.H., Lavoie, P. (2002). Architecture and Performance Characterization of Hardware and Software Implementations of the Crozier Frequency Estimation Algorithm. 2002 IEEE International Symposium on Circuits and Systems, v. 4, p. 823-826. 
225Loiseau, L., Savaria, Y. (2002). Methodologies and Strategies for Effective Design Reuse. Revue canadienne de génie électrique et informatique, 27(4), p. 165-169. 
226Meunier, A., Gagnon, Y., Savaria, Y., Lacourse, A., Cadotte, M. (2002). A Novel Laser Trimming Technique for Microelectronics. Applied Surface Science, 186(1-4), p. 52-56. 
227Meunier, M., Gagnon, Y., Savaria, Y., Lacourse, A. (2002). Laser Tuning Silicon Microdevices for Analogue Microelectronics. Opto Canada. SPIE Regional Meeting on Optoelectronics, Photonics, and Imaging, p. 205-208. 
228Renaud, M., Savaria, Y. (2002). A Linear Phase Detector for Arbitrary Clock Signals. 2002 IEEE International Symposium on Circuits and Systems, v. 4, p. 775-778. 
229Zhong-Fang Jin, Laurin, J.-J., Savaria, Y. (2002). A Practical Approach to Model Long MIS Interconnects in VLSI Circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10(4), p. 494-507. 
230Boyer, F.R., Aboulhamid, E.M., Savaria, Y., Boyer, M. (2001). Optimal Design of Synchronous Circuits Using Software Pipelining Techniques. ACM Transactions on Design Automation of Electronic Systems, 6(4), p. 516-532. 
231Calbaza, D.E., Savaria, Y. (2001). Direct Digital Frequency Synthesis of Low-Jitter Clocks. IEEE Journal of Solid-State Circuits, 36(3), p. 570-572. 
232Cantin, M.-A., Savaria, Y., Prodanos, D., Lavoie, P. (2001). An Automatic Word Length Determination Method. ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems, v. 5, p. 53-56. 
233Chabini, N., Aboulhamid, E.M., Savaria, Y. (2001). Fast Method for Determining an Efficient Bound on the Optimal Solution of the Cost-to-Time Ratio Problem. 5th World Multiconference on Systemics, Cybernetics and Informatics (SCI'2001) Et 7th International Conference in Information Systems Analysis and Synthesis (ISAS'2001), v. VII, p. 195-200. 
234Chabini, N., Aboulhamid, E.M., Savaria, Y. (2001). Reducing Register and Phase Requirements for Synchronous Circuits Derived Using Software Pipeling Techniques. IEEE Computer Society Workshop on VLSI 2001, p. 71-77. 
235Chabini, N., Aboulhamid, El.M., Savaria, Y. (2001). Minimizing Registe Requirements for Synchronous Circuits Derived Using Software Pipelining Techniques. 13th International Conference on Microelectronics (ICM'2001), p. 249-252. 
236Chabini, N., Aboulhamid, M., Savaria, Y. (2001). Determining Schedules for Reducing Power Consuption Using Mulyiple Supply Voltages. International Conference on Computer Design (ICCD'2001), p. 546-552. 
237Chabini, N., Aboulhamid, M., Savaria, Y. (2001). Efficient Methods for Reducing Register and Phase Requirements for Synchronous Circuits Derived Using Software Pipeling Techniques. European Conference on Circuit Theory and Design, v. 2, p. 237-240. 
238Chabini, N., Savaria, Y. (2001). Methods for Optimizating Register Placement in Synchronous Circuits Derived Using Software Pipelining Techniques. 14th International Symposium on System Synthesis (ISSS'2001), p. 209-214. 
239Fouzar, Y., Savaria, Y., Sawan, M. (2001). New Controlled Loop Gain Phase-Locked Loop Technique. IEEE-ISCAS.
240Fouzar, Y., Savaria, Y., Sawan, M. (2001). A New Controlled Gain Phase-Locked Loop Technique. ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems, v. 4, p. 810-813. 
241Gagnon, Y., Meunier, M., Savaria, Y. (2001). Method and Apparatus for Iteratively, Selectively Tuning the Empedance of Integrated Semiconductor Devices Using a Focussed Heating Source. (Brevet Patent - US 6329272).
242Granger, É., Savaria, Y., Lavoie, P. (2001). A Pattern Reordering Approach Based on Ambiguity Detection for on-Line Category Learning. (Rapport technique EPM RT ; 01-02). 40 p.
243Meunier, M., Gagnon, Y., Savaria, Y., Lacourse, A., Cadotte, M. (2001). A Novel Laser Trimming Technique for Microelectronics. Laser Applications in Microelectronic and Optoelectronic Manufacturing VI, p. 385-392. 
244Monte, G., Antaki, B., Patenaude, S., Savaria, Y., Thibeault, C., Trouborst, P. (2001). Tools for the Characterization of Bipolar CML Testability. Proceedings 19th IEEE VLSI Test Symposium. VTS 2001, p. 388-395. 
245Nekili, M., Savaria, Y., Bois, G. (2001). Minimizing Process-Induced Skew Using Elay Tuning. ISCAS 2001, v. 4, p. 426-429. 
246Thériault, L., Audet, D., Savaria, Y. (2001). Performance Estimators for Hardware/Software Co-Design. ISCAS 2001, v. 5, p. 17-20. 
247Adham, S.M.I., Savaria, Y., Antaki, B., Xiong, N. (2000). Voltage Excursion Detection Apparatus. (Brevet Patent - US 6100716).
248Boyer, F.R., Aboulhamid, E.M., Savaria, Y. (2000). Efficient Verification Method for a Class of Multi-Phase Sequential Circuits. IEEE ICECS2K, p. 510-515. 
249Calbaza, D.E., Savaria, Y. (2000). Jitter Model of Direct Digital Synthesis Clock Generators. TCAS-I 2000.
250Calbaza, D.E., Savaria, Y. (2000). Direct Digital Frequency Synthesis of Low-Jitter Clocks. Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, p. 31-34. 
251Calbaza, D.E., Savaria, Y. (2000). A Direct Digitally Delay Generator. 2000 International Semiconductor Conference. 23rd Edition. CAS 2000 Proceedings, p. 87-90. 
252Cantin, M.-A., Blaquière, Y., Savaria, Y., Lavoie, P., Granger, É. (2000). Analysis of Quantization Effects in a Digital Hardware Implementation of a Fuzzy ART Neural Network Algorithm. ISCAS 2000 Geneva. 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings, v. 3, p. 141-144. 
253Donfack, C., Sawan, M., Savaria, Y. (2000). Fully Integrated AC Impedance Measurement Technique for Implantable Electrical Stimulation Applications. IFESS.
254Donfack, C., Sawan, M., Savaria, Y. (2000). Techniques de caractérisation de l'interface électrode-tissus. 2nd Symposium on Advanced Biomaterials (ISAB).
255Donfack, C., Sawan, M., Savaria, Y. (2000). Implantable Measurement Technique Dedicated to the Monitoring of Electrode-Nerve Contact in Bladder Stimulators. Medical & Biological Engineering & Computing, 38(4), p. 465-468. 
256Fouzar, Y., Sawan, M., Savaria, Y. (2000). CMOS Wide-Swing Differential VCO for Fully Integrated Fast PLL. Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems, p. 948-950. 
257Fouzar, Y., Sawan, M., Savaria, Y. (2000). A New Fully Integrated CMOS Phase-Locked Loop With Low Jitter and Fast Lock Time. ISCAS 2000 Geneva. 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings, v. 2, p. 253-256. 
258Fouzar, Y., Sawan, M., Savaria, Y. (2000). Very Short Locking Time PLL Based on Controlled Gain Technique. ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems, p. 252-255. 
259Hébert, O., Kraljic, I.C., Savaria, Y. (2000). A Method to Derive Application-Specific Embedded Processing Cores. Proceedings of the Eighth International Workshop on Hardware, p. 88-92. 
260Nsame, P., Grou-Szabo, R., Savaria, Y. (2000). INTIME: a Multi-Tool Specification Environment for Ensuring Timing Constraints Integrity for SOC Design. IP Based Design 2000, p. 139-144. 
261Planque, F., Kraljic, I., Savaria, Y. (2000). Mapping Irregular Algorithms in a Custom Computing Image Processing Framework. MAPLD'2000.
262Vado, P., Savaria, Y., Zoccarato, Y., Robach, C. (2000). A Methodology for Validating Digital Circuits With Mutation Testing. ISCAS 2000 Geneva. 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings, p. 343-346. 
263Antaki, B., Savaria, Y., Saman, A., Xiong, N., Borrione, D., Ernst, R. (1999). Design for Testability Method for CML Digital Circuits. Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings, p. 360-367. 
264Bosi, B., Bois, G., Savaria, Y. (1999). Reconfigurable Pipelined 2-D Convolvers for Fast Digital Signal Processing. IEEE Transactions on Very Large Scale Integration (Vlsi) Systems, 7(3), p. 299-308. 
265Calbaza, D.E., Savaria, Y. (1999). Jitter Model of Direct Digital Synthesis Clock Generators. Proceedings - IEEE International Symposium on Circuits and Systems, v. 1, p. 1-4. 
266Cousineau, C., Laperle, F., Savaria, Y., Pocek, K.L., Arnold, J.M. (1999). Design of a JTAG Based Run Time Reconfigurable System. Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines, p. 268-269. 
267Donfack, C., Sawan, M., Savaria, Y. (1999). Efficient Monitoring of Electrodes-Nerve Contacts During FNS of the Bladder. Int. Functional Electrical Stimulation Society (IFESS).
268Jiang, Y., Tang, Y., Wang, Y., Savaria, Y. (1999). Evaluating the Ouptput Probability of Boolean Functions Without Floating Point Operations. CCCECE, p. 433-437. 
269Jin, Z.-F., Laurin, J.-J., Savaria, Y. (1999). New Approach to Analyze Interconnect Delays in RC Wire Models. Proceedings - IEEE International Symposium on Circuits and Systems, v. 6, p. 246-249. 
270Lavoie, P., Crespo, J.F., Savaria, Y. (1999). Generalization, Discrimination, and Multiple Categorization Using Adaptive Resonance Theory. IEEE Transactions on Neural Networks, 10(4), p. 757-767. 
271Le Chapelain, B., Mechain, A., Savaria, Y., Bois, G. (1999). Development of a High Performance TSPC Library for Implementation of Large Digital Building Blocks. ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems. VLSI, v. 1, p. 443-446. 
272Nekili, M., Savaria, Y., Bois, G. (1999). Spatial Characterization of Process Variations Via Mos Transistor Time Constants in Vlsi and Wsi. IEEE Journal of Solid-State Circuits, 34(1), p. 80-84. 
273Nsame, P., Savaria, Y. (1999). Virtualising on-Chip Bus Interfaces for Improved Embedded Processor System Performance. IFIP International Workshop on IP Based Synthesis and System Design 1999, p. 138-143. 
274Audet, D., Masson, S., Savaria, Y. (1998). Reducing Fault Sensitivity of Microprocessor-Based System by Modifying Workload Structure. IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, p. 241-249. 
275Boyer, F.R., Abiylhamid, E.M., Savaria, Y., Bennour, I.E. (1998). Optical Design of Synchronous Circuits Using Software Pipeling Techniques. VLSI in Computers and Processors, p. 62-67. 
276Cantin , M.-A., Blaquière, Y., Savaria, Y., Granger, E., Lavoie, P. (1998). Implementation Fo the Fuzzy ART Neural Network for Fast Clustering of Radar Pulses. ISCAS 98, p. 14-17. 
277Chabini, N., Bennour, I.E., Aboulhamid, E.M., Savaria, Y. (1998). Static Method for System Performance Estimation. 10th International Conference on Microelectronics.
278Fouzar, Y., Sawan, M., Savaria, Y. (1998). A BiCMOS Wide-Lock Range Fully Integrated PLL. Proceedings of the Tenth International Conference on Microelectronics, p. 274-277. 
279Granger, É., Savaria, Y., Lavoie, P., Cantin, M.A. (1998). Comparison of Self-Organizing Neural Networks for Fast Clustering of Radar Pulses. Signal Processing, 64(3), p. 249-269. 
280Marriott, P., Kraljic, I., Savaria, Y. (1998). Parallel Ultra Large Scale Engine SIMD Architectures for Real Time Digital Signal Processing Applications. ICCD'98, p. 482-487. 
281Nekili, M., Savaria, Y., Bois, G., Bayoumi, M.A., Jullien, G. (1998). Design of Clock Distribution Networks in Presence of Process Variations. Proceedings of the 8th Great Lakes Symposium on VLSI, p. 95-102. 
282Poire, P., Cantin, M.-A., Daniel, H., Blaquiere, Y., Savaria, Y., Pocek, K.L., Arnold, J.M. (1998). A Comparative Analysis of Fuzzy ART Neural Network Implementations: the Advantages of Reconfigurable Computing. Proceedings IEEE Symposium on FPGAs for Custom Computing Machines, p. 304-305. 
283Poire, P., Savaria, Y., Daniel, H., Cantin, M.a., Blaquiere, Y. (1998). Hardware/Software Codesign of a Fuzzy ART Neural Clusterer : The Benefits of Configurable Computing. Configurable Computing : Technology and Applications. Papers From the Third Conference on Configurable Computing, p. 90-96. 
284Savaria, Y., El Hassan, F., Khali, H., Sawan, M. (1998). Effective Hardware/Software Implementation of a Viterbi Decoder Using an FPGA-Based Reconfigurable Computing Platform. FDP'98, p. 161-165. 
285Savaria, Y. (1998). Study of Neural Networks for Clustering Radar Signals: Final Report. 180 p. 98-610
286Antaki, B., Patenaude, S., Trognon, L., Savaria, Y. (1997). Study on Split-Output TSPC CMOS Circuits. Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97, p. 1892-1895. 
287Bois, G., Bosi, B., Savaria, Y. (1997). High Performance Reconfigurable Coprocessor for Digital Signal Processing. 14th Annual Int. Conference Mentor Graphics Users' Group.
288Bélanger, N., Antaki, B., Savaria, Y. (1997). An Algorithm for Fast Array Transfers. Proceedings of 11th Annual International Symposium on High Performance Computing Systems, p. 117-126. 
289Gagnon, Y., Meunier, M., Savaria, Y., Thibeault, C. (1997). Mathematical Cost Model for Redundant Multi-Processor Arrays. Journal of Microelectronic Systems Integration, 5(4), p. 199-208. 
290Gagnon, Y., Savaria, Y., Meunier, M., Thibeault, C. (1997). Are Defect-Tolerant Circuits With Redundancy Really Cost-Effective? Complete and Realistic Cost Model. Proceedings of the 1997 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, p. 157-165. 
291Granger, É., Savaria, Y., Blaquière, V., Cantin, M.-A., Lavoie, P. (1997). A VLSI Architecture for Fast Clustering With Fuzzy ART Neural Networks. Journal of Microelectronic Systems Integration, 5(1), p. 3-18. 
292Hrytzak, R., Savaria, Y., Goslin, G. (1997). Reconfigurable Computing Greatly Simplifies System Development. DSP World Spring Design Conference, p. 271-286. 
293Kafrounni, M., Thibeault, C., Savaria, Y. (1997). Cost Model for VLSI/MCM Systems. IEEE Symposium on Defect and Fault Tolerance in VLSI Systems, p. 148-156. 
294Khali, H., Savaria, Y., Houle, J.L. (1997). Computational Limits of Homogeneous Acceleration Using Lookup Tables. Proceedings of 11th Annual International Symposium on High Performance Computing Systems, p. 345-351. 
295Lavoie, P., Crespo, J.F., Savaria, Y. (1997). Multiple Categorization Using Fuzzy ART. ICNN'1997, p. 1983-1988. 
296Nekili, M., Bois, G., Savaria, Y. (1997). Pipelined H-Trees for High-Speed Clocking of Large Integrated Systems in Presence of Process Variations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 5(2), p. 161-174. 
297Pera, F., Savaria, Y., Bois, G. (1997). Time Delay Measurement Methods for Integrated Transmission Lines and High Speed Cells Characterization. Proceedings of the 1997 IEEE International Symposium on Circuits and Systems, ISCAS'97, p. 293-296. 
298Abderrahman, A., Savaria, Y., Kaminska, B. (1996). Analyse, estimation et réduction du bruit de commutation simultanee. Revue canadienne de génie électrique et informatique, 21(4), p. 133-143. 
299Audet, D., Gagnon, F., Savaria, Y. (1996). Quantitative Comparisons of TMR Implementations in a Multiprocessor System. 3nd IEEE on-Lne Testing Workshop, p. 196-199. 
300Audet, D., Gagnon, N., Savaria, Y. (1996). Implementing Fault Injection and Tolerance Mechanisms in Multiprocessor Systems. IEEE Workshop on Defect and Fault Tolerance in VLSI, p. 310-317. 
301Belabbes, N.-E., Guterman, A.J., Savaria, Y., Dagenais, M. (1996). Ratioed Voter Circuit for Testing and Fault-Tolerance in VLSI Processing Arrays. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 43(2), p. 143-152. 
302Belhaouane, A., Savaria, Y., Kaminska, B. (1996). Reconstruction Method for Data Acquisition Systems Qith Randomly Distributed Jitter. IEEE 2nd International Mixed Signal Testing Workshop, p. 119-122. 
303Belhaouane, A., Savaria, Y., Kaminska, B., Massicotte, D. (1996). Reconstruction Method for Jitter Tolerant Data Acquisition System. Journal of Electronic Testing: Theory and Applications (JETTA), 9(1-2), p. 177-185. 
304Blaquiere, Y., Dagenais, M., Savaria, Y. (1996). Timing Analysis Speed-Up Using a Hierarchical and a Multimode Approach. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(2), p. 244-255. 
305Granger, É., Blaquière, Y., Savaria, Y., Cantin, M.-A., Lavoie, P. (1996). VLSI Architecture for Fast Clustering With Fuzzy ART Neural Networks. Proceedings of the 1996 1st International Workshop on Neural Networks for Identification, Control, Robotics, and Signal, p. 117-125. 
306Lavoie, P., Crespo, J.-F., Savaria, Y. (1996). On the Stability of Fuzzy ART. 18th Biennal Symposium on Communications, p. 185-188. 
307Lejmi, S., Bois, G., Savaria, Y. (1996). On the Effects of Retiming Applied to Self-Checking Sequential Circuit. 2nd IEEE on-Line Testing Workshop, p. 96-99. 
308Savaria, Y., Bois, G., Popovic, P., Wayne, A. (1996). Computational Acceleration Methodologies: Advantages of Reconfigurable Acceleration Subsystems. High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic, p. 195-205. 
309Savaria, Y., Thibeault, C., Ivanov, A. (1996). Ieee Vlsi Test Symposium - Meeting the Quality Challenge. IEEE Design & Test of Computers, 13(3), p. 110-112. 
310Soufi, M., Rochon, S., Savaria, Y., Kaminska, B. (1996). Design and Performance of CMOS TSPC Cells for High Speed Pseudo Random Testing. Proceedings of the 1996 14th IEEE VLSI Test Symposium, p. 368-373. 
311St-Amand, R., Sawan, M., Savaria, Y. (1996). Design and Optimization of a Low DC Offset CMOS Current-Source Dedicated to Implantable Miniaturized Stimulators. Analog Integrated Circuits and Signal Processing, 11(1), p. 47-61. 
312Audet, D., Savaria, Y. (1995). High-Speed Interconnections Using True Single-Phase Clocking. Journal of Microelectronic Systems Integration, 3(4), p. 247-257. 
313Audet, D., Savaria, Y. (1995). Effective Ultra Large Scale Integration (ULSI) Architecture Techniques : the Host Interface. 61 p.
314Audet, D., Savaria, Y. (1995). Effective Ultra Large Scale Integration (ULSI) Architecture Techniques : the Routers, From a Functional to a Detailed Implementation Description. 123 p.
315Audet, D., Savaria, Y. (1995). High-Speed Interconnections Using True Single-Phase Clocking. 1995 Proceedings : 7th Annual IEEE International Conference on Wafer Scale Integration, p. 258-267. 
316Audet, D., Savaria, Y., Arel, N. (1995). Effective Ultra Large Scale Integration (ULSI) Architecture Techniques: FATMOS, a Fault-Tolerant Multiprocessor Operating System. 36 p.
317Barwicz, A., Massicotte, D., Savaria, Y., Pango, P.A., Morawski, R.Z. (1995). An Application-Specific Processor Dedicated to Kalman-Filter-Based Correction of Spectrometric Data. IEEE Transactions on Instrumentation and Measurement, 44(3), p. 720-724. 
318Belzile, J., Savaria, Y., Haccoun, D., Chalifoux, M. (1995). Bounds on the Performance of Partial Selection Networks. IEEE Transactions on Communications, 43(2-4), p. 1800-1809. 
319Blaquiere, T., Gagné, G., Savaria, Y., Evequoz, C. (1995). A New Efficient Algorithmic-Based Seu Tolerant System Architecture. IEEE Transactions on Nuclear Science, 42(6), p. 1599-1606. 
320Gadiri, A., Savaria, Y., Kaminska, B. (1995). Optimized CMOS Compatible Photoreceiver. Proceedings of the 1995 Canadian Conference on Electrical and Computer Engineering, p. 211-214. 
321Kermouche, R., Audet, D., Savaria, Y. (1995). On the Optimization of Integrated Hierarchical Bus Architectures to Achieve Efficient Fault-Tolerance. Journal of Microelectronic Systems Integration, 3(1), p. 47-63. 
322Khali, H., Savaria, Y., Houle, J.L., Beraldin, J.A., Blais, F., Rioux, M. (1995). VLSI Chip for 3-D Camera Calibration. Proceedings of the 1995 Canadian Conference on Electrical and Computer Engineering, p. 120-123. 
323Rzeszut, J., Kaminska, B., Savaria, Y. (1995). New Method for Testing Mixed Analog and Digital Circuits. Proceedings of the 1995 4th Asian Test Symposium, p. 127-132. 
324Sawan, M., St-Amand, R., Savaria, Y. (1995). Design and Optimization of Programmable Biphasic Current-Sources. Proceedings of Second Annual International Conference on Electronics, Circuits and Systems. ICECS'95, p. 169-173. 
325Soufi, M., Savaria, Y., Darlay, F., Kaminska, B. (1995). Producing Reliable Initialization and Test of Sequential Circuits With Pseudorandom Vectors. IEEE Transactions on Computers, 44(10), p. 1251-1256. 
326Soufi, M., Savaria, Y., Kaminska, B. (1995). On the Design of at-Speed Testable VLSI Circuits. Proceedings of the 13th IEEE VLSI Test Symposium, p. 290-295. 
327Soufi, M., Savaria, Y., Kaminska, B. (1995). On Using Partial Reset for Pseudo-Random Testing. Proceedings of the 1995 IEEE International Symposium on Circuits and Systems-ISCAS 95, p. 949-952. 
328Thibeault, C., Savaria, Y., Houle, J.L. (1995). Equivalence Proofs of Some Yield Modeling Methods for Defect-Tolerant Integrated-Circuits. IEEE Transactions on Computers, 44(5), p. 724-728. 
329Abderrahman, A., Kaminska, B., Savaria, Y. (1994). Estimation of Simultaneous Switching Power and Ground Noise of Static CMOS Combinational Circuits. Proceedings of the European Design and Test Conference, p. 658. 
330Audet, D., Savaria, Y. (1994). Architectural Approach for Increasing Clock Frequency and Communication Speed in Momolithic WSI Systems. IEEE Transactions on Components Packaging and Manufacturing Technology. Part B, Advanced Packaging, 17(3), p. 362-368. 
331Audet, D., Savaria, Y., Arel, N. (1994). Architectural Approach for Increasing Clock Frequency and Communication Speed in Monolithic-WSI Systems. 6th Annual IEEE International Conference on Wafer Scale Integration, p. 235-243. 
332Audet, D., Savaria, Y., Arel, N. (1994). Pipelining Communications in Large VLSI/ULSI Systems. IEEE Transactions on Very Large Scale Integration (VLsi) Systems, 2(1), p. 1-10. 
333Barwicz, A., Massicotte, D., Savaria, Y., Santerre, M.A., Morawsi, R.Z. (1994). Application-Specific Processor Dedicated to Kalman-Filter-Based Correction Od Spectrometric Data. IMTC'94, p. 352-356. 
334Barwicz, A., Massicotte, D., Savaria, Y., Santerre, M.A., Morawski, R.Z. (1994). An Integrated Structure for Kalman-Filter-Based Measurand Reconstruction. IEEE Transactions on Instrumentation and Measurement, 43(3), p. 403-410. 
335BenHamida, N., Kaminska, B., Savaria, Y. (1994). Pseudo-Random Vector Compaction for Sequential Testability. Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, p. 63-66. 
336Bélanger, N., Haccoun, D., Savaria, Y. (1994). A Multiprocessor Architecture for Multiple Path Stack Sequential Decoders. IEEE Transactions on Communications, 42(2-4, pt.2), p. 951-957. 
337Crespo, J.-F., Lavoie, P., Savaria, Y. (1994). Fast Convergence With Low Precision Weights in ART1 Networks. Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, p. 237-240. 
338Ghannoum, S., Chtchvyrkov, D., Savaria, Y. (1994). Comparative Study of Single-Phase Clocked Latches Using Estimation Criteria. Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, p. 347-350. 
339Ghannoum, S., Chtchvyrkov, D., Savaria, Y. (1994). Single-Clock Dynamic Latches Optimization. Proceedings of the 37th Midwest Symposium on Circuits and Systems, p. 46-49. 
340Kermouche, R., Savaria, Y., Audet, D. (1994). Harvest Model of an Integrated Hierarchical-Bus Architecture. Proceedings of the 6th Annual IEEE International Conference on Wafer Scale Integration, p. 69-78. 
341Kermouche, R., Savaria, Y. (1994). Defect and Fault Tolerant Scan Chains. Proceedings of the 1994 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, p. 185-193. 
342Kroumba, S.M., Bois, G., Savaria, Y. (1994). Synthesis Approach for the Generation of Parallel Architectures. Proceedings of the 37th Midwest Symposium on Circuits and Systems, p. 323-326. 
343Lavoie, P., Haccoun, D., Savaria, Y. (1994). Systolic Architecture for Fast Stack Sequential Decoders. IEEE Transactions on Communications, 42(2), p. 324-335. 
344Nekili, M., Savaria, Y., Bois, G. (1994). Fast Low-Power Driver for Long Interconnections in VLSI Systems. IEEE 1994 International Symposium on Circuits and Systems (ISCAS'94), v. 4, p. 343-346. 
345Nekili, M., Savaria, Y., Bois, G. (1994). A Variable-Size Parallel Regenerator for Long Integrated Interconnections. Proceedings of 1994 37th Midwest Symposium on Circuits and Systems, v. 1, p. 50-53. 
346Nekili, M., Bois, G., Savaria, Y. (1994). Deterministic Skew Modeling and High-Speed Clocking of Large Integrated Systems by Using Logic-Based & Hybrid H-Trees. (Rapport technique EPM RT ; 94-09). 46 p.
347Savaria, Y. (1994). Parallel Microprocessor Architecture. (Brevet Patent - US 5276893).
348Savaria, Y., Chtchvyrkov, D., Currie, J.F. (1994). Fast CMOS Voltage-Controlled Ring Oscillator. Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, p. 359-362. 
349St.-Amand, R., Sawan, M., Savaria, Y. (1994). Generation of Balanced Bipolar Stimuli Based on Current Sources Without Coupling Capacitor. Proceedings of 16th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, v. 2, p. 992-993. 
350St-Amand, R., Savaria, Y., Sawan, M. (1994). Design Optimization of a Current Source for Microstimulator Applications. Proceedings of the 37th Midwest Symposium on Circuits and Systems, p. 129-132. 
351Thibeault, C., Savaria, Y., Houle, J.L. (1994). A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated-Circuits. IEEE Transactions on Computers, 43(6), p. 687-697. 

 

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