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Journal article (4) Conference paper (25) Book Book chapter Patent Report (1) Thesis

François-Raymond Boyer (30)

  • Journal articles (4)
    • 2011
      • Journal article
        Hosseini, P., Martins, S., Martin, T., Radziszewski, P. & Boyer, F.-R. (2011). Acoustic emissions simulation of tumbling mills using charge dynamics. Minerals Engineering, 24(13), 1440-1447.
    • 2006
      • Journal article
        Boyer, F.R., Epassa, H.G. & Savaria, Y. (2006). Embedded power-aware cycle by cycle variable speed processor. IEE Proceedings. Computers and Digital Techniques, 153(4), 283-290.
    • 2004
      • Journal article
        Lapalme, J., Aboulhamed, E.M., Nicolescu, G., Charest, L., Boyer, F.R., David, J.P. & Bois, G. (2004). Esys.net: A New Solution for Embedded Systems Modeling and Simulation. ACM Sigplan Notices, 39(7), 107-114. Retrieved from https://doi.org/10.1145/997163.997179
    • 2001
      • Journal article
        Boyer, F.R., Aboulhamid, E.M., Savaria, Y. & Boyer, M. (2001). Optimal Design of Synchronous Circuits Using Software Pipelining Techniques. ACM Transactions on Design Automation of Electronic Systems, 6(4), 516-532.
  • Conference papers (25)
    • 2018
      • Conference paper
        Benacer, I., Boyer, F.-R. & Savaria, Y. (2018). Design of a low latency 40 Gb/s flow-based traffic manager using high-level synthesis. Paper presented at the IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy (5 pages). Retrieved from https://doi.org/10.1109/ISCAS.2018.8351332
      • Conference paper
        Santiago da Silva, J., Boyer, F.-R., Chiquette, L.-O. & Langlois, J.M.P. (2018). Extern objects in P4: an ROHC compressing scheme case study. Paper presented at the IEEE Conference on Network Softwarization (NetSoft 2018), Montréal, QC.
      • Conference paper
        Santiago da Silva, J., Boyer, F.-R. & Langlois, J.M.P. (2018). P4-compatible high-level synthesis of low latency 100 Gb/s streaming packet parsers in FPGAs. Paper presented at the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2018), Monterey, California, USA (pp. 147-152). Retrieved from https://doi.org/10.1145/3174243.3174270
    • 2017
      • Conference paper
        Benacer, I., Boyer, F.-R. & Savaria, Y. (2017). A high-speed traffic manager architecture for flow-based networking. Paper presented at the 15th IEEE International New Circuits and Systems Conference (NEWCAS 2017), Strasbourg, France (pp. 161-164). Retrieved from https://doi.org/10.1109/NEWCAS.2017.8010130
    • 2016
      • Conference paper
        Benacer, I., Boyer, F.-R., Bélanger, N. & Savaria, Y. (2016). A fast systolic priority queue architecture for a flow-based Traffic Manager. Paper presented at the 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages). Retrieved from https://doi.org/10.1109/NEWCAS.2016.7604761
      • Conference paper
        Lacroix, A.B., Langlois, J.M.P., Boyer, F.-R., Gosselin, A. & Bois, G. (2016). Node configuration for the Aho-Corasick algorithm in intrusion detection systems. Paper presented at the 12th ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS 2016), Santa Clara, California (pp. 121-122). Retrieved from https://doi.org/10.1145/2881025.2889473
      • Conference paper
        Alizadeh, R., Belanger, N., Savaria, Y. & Boyer, F.R. (2016). Performance characterization of an SCMA decoder. Paper presented at the 14th IEEE International New Circuits and Systems Conference (NEWCAS 2016), Vancouver, Canada (4 pages). Retrieved from https://doi.org/10.1109/NEWCAS.2016.7604820
    • 2010
      • Conference paper
        Njinowa, M.S., Bui, H.T. & Boyer, F.-R. (2010). Peak-to-peak jitter reduction technique for the Free-Running Period Synthesizer (FRPS). Paper presented at the IEEE International Symposium on Circuits and Systems. ISCAS 2010, Paris, France (pp. 1312-1315).
    • 2009
      • Conference paper
        Njinowa, M.S., Bui, H.T. & Boyer, F.-R. (2009). Design and optimization of a low complexity all-digital digital-to-analog converter. Paper presented at the Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France.
      • Conference paper
        Vezant, B., Mansuy, C., Bui, H.T. & Boyer, F.-R. (2009). Direct digital synthesis-based all-digital phase-locked loop. Paper presented at the Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2009), Toulouse, France (pp. 43-46).
      • Conference paper
        Trabelisi, A., Boyer, F.R. & Boukadoum, M. (2009). Robust Estimation of LP Parameters in White Noise with Unknown Variance. Paper presented at the 16th IEEE International Conference on Electronics, Circuits and Systems, Medina, Tunisia (pp. 335-338).
    • 2008
      • Conference paper
        Pontikakis, B., Bui, H.T., Boyer, F.-R. & Savaria, Y. (2008). A novel phase-locked loop (PLL) architecture without an analog loop filter for better integration in ultra-deep submicron SoCs. Paper presented at the Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA 2008) (pp. 363-366).
    • 2007
      • Conference paper
        Pontikakis, B., Bui, H.T., Boyer, F.-R. & Savaria, Y. (2007). A low-complexity high-speed clock generator for dynamic frequency scaling of FPGA and standard-cell based designs. Paper presented at the IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, LA, United States (pp. 633-636).
      • Conference paper
        Trabelisi, A., Boyer, F.R., Savaria, Y. & Boukadoum, M. (2007). Improving LPC Analysis of Speech in Additive Noise. Paper presented at the IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007), Montréal, Canada (pp. 93-96).
      • Conference paper
        Trabelisi, A., Boyer, F.R., Savaria, Y. & Boukadoum, M. (2007). Iterative Noise-Compensated Method to Improve LPC Based Speech Analysis. Paper presented at the 14h IEEE International Conference on Electronics, Circuits & Systems, Marrakech, Morocco (pp. 1364-1367).
      • Conference paper
        Pontikakis, B., Boyer, F.-R., Savaria, Y. & Bui, H.T. (2007). Precise free-running period synthesizer (FRPS) with process and temperature compensation. Paper presented at the 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007) (pp. 1118-1121).
      • Conference paper
        Trabelsi, A., Boyer, F.R. & Savaria, Y. (2007). Speech enhancement based noise PSD estimator to remove cosine shaped residual noise. Paper presented at the 50th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2007) (pp. 393-396).
    • 2006
      • Conference paper
        Pontikakis, B., Boyer, F.-R. & Savaria, Y. (2006). A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs. Paper presented at the IEEE International Symposium on Circuits and Systems (ISCAS 2006), Island of Kos, Greece (pp. 1259-1262).
    • 2005
      • Conference paper
        Epassa, H.G., Boyer, F.R. & Savaria, Y. (2005). Implementation of a Cycle by Cycle Variable Speed Processor. Paper presented at the IEEE International Symposium on Circuits and Systems (ISCAS 2005), Kobe, Japan (pp. 3335-3338).
      • Conference paper
        Pontikakis, B., Boyer, F.R. & Savaria, Y. (2005). Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period. Paper presented at the 5th International Workshop on System on Chip for Real-Time Applications (IWSOC 2005), Banff, Alberta, Canada (pp. 454-458).
    • 2004
      • Conference paper
        Boyer, F.-R., Epassa, H.G., Pontikakis, B., Savaria, Y. & Ling, W. (2004). A variable period clock synthesis (VPCS) architecture for next-generation power-aware SoC applications. Paper presented at the 2nd annual IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2004), Montréal (pp. 145-148).
      • Conference paper
        Lapalme, J., Aboulhamid, E.M., Nicolescu, G., Charest, L., Boyer, F.R., David, J.P. & Bois, G. (2004). Robust Estimation of LP Parameters in White Noise with Unknown Variance. Paper presented at the Design, Automation and Test in Europe Conference and Exhibition (DATE 2004), Paris, France (pp. 732-733).
      • Conference paper
        Chevalier, J., Benny, O., Rondonneau, M., Bois, G., Aboulhamid, E.M. & Boyer, F.R. (2004). Space: a Hardware/Software Systemc Modeling Platform Including an Rtos. Paper presented at the Forum on Specification and Design Languages (FDL 2003) (pp. 91-104).
    • 2003
      • Conference paper
        Boyer, F.R., Yang, L., Aboulamid, E.M., Charest, L. & Nicolescu, G. (2003). Multiple SimpleScalar Processors with Introspection, under SystemC. Paper presented at the 46th IEEE Midwest Symposium on Circuits and Systems (MWSCAS 2003), Cairo, Egypt (pp. 1400-1404).
    • 2002
      • Conference paper
        Li, J., Boyer, F.R. & Aboulhamid, E.M. (2002). Retargetable C Compiler for Network Processors. Paper presented at the 6th World Multiconference on Systemics, Cybernetics and Informatics, Orlando, Florida (pp. 445-448).
  • Reports (1)
    • 2006
      • Report
        Trabelsi, A., Boyer, F.-R. & Savaria, Y. (2006). On the application of minimum noise tracking to cancel cosine shaped residual noise (Report No EPM-RT-2006-09). École Polytechnique de Montréal. Retrieved from https://publications.polymtl.ca/3157/